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a788e3d436
BREAKING CHANGE: STM32N6 non-standard hardware definition macros (IRQ, peripheral-count, SRAM and related) were renamed to the common STM32_* prefix. Out-of-tree code must update the affected references. Signed-off-by: raiden00pl <raiden00@railab.me>
69 lines
2.9 KiB
C
69 lines
2.9 KiB
C
/****************************************************************************
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* arch/arm/include/stm32n6/chip.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_STM32N6_CHIP_H
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#define __ARCH_ARM_INCLUDE_STM32N6_CHIP_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Prototypes
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****************************************************************************/
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/* Memory sizes - STM32N6 has no internal flash. Code runs from the
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* on-chip AXI SRAM (loaded by the debugger in DEV mode, or by an FSBL
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* from external XSPI flash in normal boot).
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*
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* AXI SRAM layout (from CMSIS stm32n657xx.h):
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* AXISRAM1: 0x34000000 1 MB
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* AXISRAM2: 0x34100000 1 MB
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* AXISRAM3: 0x34200000 448 KB
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* AXISRAM4: 0x34270000 448 KB
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* AXISRAM5: 0x342E0000 448 KB
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* AXISRAM6: 0x34350000 448 KB
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* CACHEAXIRAM: 0x343C0000 256 KB
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* -------------------------------------------
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* Total: 4 MB (end = 0x34400000)
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*
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* VENCRAM (128 KB at 0x34400000) is excluded -- reserved for video encoder.
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* Each bank requires its RCC MEMENR clock enable bit to be set.
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*/
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#define STM32_SRAM_SIZE (4 * 1024 * 1024) /* 4194304 bytes (4 MiB) */
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#define STM32_NPORTS (12) /* GPIO ports A-H (8) + N, O, P, Q (4) */
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#define STM32_NUSART (1) /* USART1 */
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/* NVIC priority levels *****************************************************/
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/* 16 Programmable interrupt levels (4-bit priority) */
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#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */
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#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
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#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */
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#endif /* __ARCH_ARM_INCLUDE_STM32N6_CHIP_H */
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