mirror of
https://github.com/apache/nuttx.git
synced 2026-10-03 04:07:55 +00:00
07c4bf0048
Move the stm32l1 sources, headers and boards into arch/arm/src/stm32l1, arch/arm/include/stm32l1 and boards/arm/stm32l1, then finalize the split: source each split family directly in arch/arm/Kconfig and boards/Kconfig and remove the now-empty combined arch/arm/src/stm32 and boards/arm/stm32 trees. BREAKING CHANGE: The legacy STM32 architecture and board paths were split into stm32f1, stm32l1, stm32f2, stm32f3, stm32f4, and stm32g4 directories. Out-of-tree boards must move from stm32 to the matching split family. Signed-off-by: raiden00pl <raiden00@railab.me>
491 lines
30 KiB
C
491 lines
30 KiB
C
/****************************************************************************
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* arch/arm/include/stm32l1/chip.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_STM32L1_CHIP_H
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#define __ARCH_ARM_INCLUDE_STM32L1_CHIP_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Prototypes
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****************************************************************************/
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/* Get customizations for each supported chip and provide alternate function
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* pin-mapping
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*
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* NOTE: Each GPIO pin may serve either for general purpose I/O or for a
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* special alternate function (such as USART, CAN, USB, SDIO, etc.). That
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* particular pin-mapping will depend on the package and STM32 family. If
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* you are incorporating a new STM32 chip into NuttX, you will need to add
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* the pin-mapping to a header file and to include that header file below.
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* The chip-specific pin-mapping is defined in the chip datasheet.
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*/
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/* STM32L EnergyLite Line ***************************************************/
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/* STM32L151XX -- No LCD
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* STM32L152XX -- With LCD
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*
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* STM32L15XCX -- 48-pins
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* STM32L15XRX -- 64-pins
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* STM32L15XVX -- 100-pins
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* STM32L15XZX -- 144-pins
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*
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* STM32L15XX6 -- 32KB FLASH, 10KB SRAM, 4KB EEPROM
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* STM32L15XX8 -- 64KB FLASH, 10KB SRAM, 4KB EEPROM
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* STM32L15XXB -- 128KB FLASH, 16KB SRAM, 4KB EEPROM
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*
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* STM32L15XXC -- 256KB FLASH, 32KB SRAM, 8KB EEPROM (medium+ density)
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*
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* STM32L16XXD -- 384KB FLASH, 48KB SRAM, 12KB EEPROM (high density)
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* STM32L16XXE -- 512KB FLASH, 80KB SRAM, 16KB EEPROM (high density)
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*/
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#if defined(CONFIG_ARCH_CHIP_STM32L151C6) || defined(CONFIG_ARCH_CHIP_STM32L151C8) || \
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defined(CONFIG_ARCH_CHIP_STM32L151CB)
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# define STM32_NFSMC 0 /* No FSMC */
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# define STM32_NATIM 0 /* No advanced timers */
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# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */
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# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
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# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
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# define STM32_NDMA 1 /* DMA1, 7-channels */
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# define STM32_NSPI 2 /* SPI1-2 */
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# define STM32_NI2S 0 /* No I2S */
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# define STM32_NUSART 3 /* USART1-3 */
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# define STM32_NLPUART 0 /* No LPUART */
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# define STM32_NI2C 2 /* I2C1-2 */
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# define STM32_NCAN 0 /* No CAN */
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# define STM32_NSDIO 0 /* No SDIO */
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NGPIO 37 /* GPIOA-E,H */
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# define STM32_NADC 1 /* ADC1, 14-channels */
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# define STM32_NDAC 2 /* DAC 1, 2 channels */
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# define STM32_NCMP 2 /* (2) Comparators */
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# define STM32_NCAPSENSE 13 /* Capacitive sensing channels */
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# define STM32_NCRC 0 /* No CRC */
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# define STM32_NETHERNET 0 /* No Ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32L151R6) || defined(CONFIG_ARCH_CHIP_STM32L151R8) || \
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defined(CONFIG_ARCH_CHIP_STM32L151RB)
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# define STM32_NFSMC 0 /* No FSMC */
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# define STM32_NATIM 0 /* No advanced timers */
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# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */
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# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
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# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
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# define STM32_NDMA 1 /* DMA1, 7-channels */
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# define STM32_NSPI 2 /* SPI1-2 */
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# define STM32_NI2S 0 /* No I2S */
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# define STM32_NUSART 3 /* USART1-3 */
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# define STM32_NLPUART 0 /* No LPUART */
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# define STM32_NI2C 2 /* I2C1-2 */
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# define STM32_NCAN 0 /* No CAN */
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# define STM32_NSDIO 0 /* No SDIO */
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NGPIO 51 /* GPIOA-E,H */
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# define STM32_NADC 1 /* ADC1, 20-channels */
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# define STM32_NDAC 2 /* DAC , 2 channels */
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# define STM32_NCMP 2 /* (2) Comparators */
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# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */
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# define STM32_NCRC 0 /* No CRC */
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# define STM32_NETHERNET 0 /* No Ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32L151V6) || defined(CONFIG_ARCH_CHIP_STM32L151V8) || \
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defined(CONFIG_ARCH_CHIP_STM32L151VB)
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# define STM32_NFSMC 0 /* No FSMC */
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# define STM32_NATIM 0 /* No advanced timers */
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# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */
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# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
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# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
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# define STM32_NDMA 1 /* DMA1, 7-channels */
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# define STM32_NSPI 2 /* SPI1-2 */
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# define STM32_NI2S 0 /* No I2S */
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# define STM32_NUSART 3 /* USART1-3 */
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# define STM32_NLPUART 0 /* No LPUART */
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# define STM32_NI2C 2 /* I2C1-2 */
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# define STM32_NCAN 0 /* No CAN */
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# define STM32_NSDIO 0 /* No SDIO */
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NGPIO 83 /* GPIOA-E,H */
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# define STM32_NADC 1 /* ADC1, 24-channels */
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# define STM32_NDAC 2 /* DAC 1, 2 channels */
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# define STM32_NCMP 2 /* (2) Comparators */
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# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */
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# define STM32_NCRC 0 /* No CRC */
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# define STM32_NETHERNET 0 /* No Ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32L152C6) || defined(CONFIG_ARCH_CHIP_STM32L152C8) || \
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defined(CONFIG_ARCH_CHIP_STM32L152CB)
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# define STM32_NFSMC 0 /* No FSMC */
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# define STM32_NATIM 0 /* No advanced timers */
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# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */
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# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
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# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
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# define STM32_NDMA 1 /* DMA1, 7-channels */
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# define STM32_NSPI 2 /* SPI1-2 */
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# define STM32_NI2S 0 /* No I2S */
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# define STM32_NUSART 3 /* USART1-3 */
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# define STM32_NLPUART 0 /* No LPUART */
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# define STM32_NI2C 2 /* I2C1-2 */
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# define STM32_NCAN 0 /* No CAN */
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# define STM32_NSDIO 0 /* No SDIO */
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# define STM32_NLCD 1 /* LCD 4x18 */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NGPIO 37 /* GPIOA-E,H */
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# define STM32_NADC 1 /* ADC1, 14-channels */
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# define STM32_NDAC 2 /* DAC 1, 2 channels */
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# define STM32_NCMP 2 /* (2) Comparators */
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# define STM32_NCAPSENSE 13 /* Capacitive sensing channels */
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# define STM32_NCRC 0 /* No CRC */
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# define STM32_NETHERNET 0 /* No Ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32L152R6) || defined(CONFIG_ARCH_CHIP_STM32L152R8) || \
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defined(CONFIG_ARCH_CHIP_STM32L152RB)
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# define STM32_NFSMC 0 /* No FSMC */
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# define STM32_NATIM 0 /* No advanced timers */
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# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */
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# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
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# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
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# define STM32_NDMA 1 /* DMA1, 7-channels */
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# define STM32_NSPI 2 /* SPI1-2 */
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# define STM32_NI2S 0 /* No I2S */
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# define STM32_NUSART 3 /* USART1-3 */
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# define STM32_NLPUART 0 /* No LPUART */
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# define STM32_NI2C 2 /* I2C1-2 */
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# define STM32_NCAN 0 /* No CAN */
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# define STM32_NSDIO 0 /* No SDIO */
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# define STM32_NLCD 1 /* LCD 4x32, 8x28 */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NGPIO 51 /* GPIOA-E,H */
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# define STM32_NADC 1 /* ADC1, 20-channels */
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# define STM32_NDAC 2 /* DAC 1, 2 channels */
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# define STM32_NCMP 2 /* (2) Comparators */
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# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */
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# define STM32_NCRC 0 /* No CRC */
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# define STM32_NETHERNET 0 /* No Ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32L152V6) || defined(CONFIG_ARCH_CHIP_STM32L152V8) || \
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defined(CONFIG_ARCH_CHIP_STM32L152VB)
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# define STM32_NFSMC 0 /* No FSMC */
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# define STM32_NATIM 0 /* No advanced timers */
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# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */
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# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
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# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
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# define STM32_NDMA 1 /* DMA1, 7-channels */
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# define STM32_NSPI 2 /* SPI1-2 */
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# define STM32_NI2S 0 /* No I2S */
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# define STM32_NUSART 3 /* USART1-3 */
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# define STM32_NLPUART 0 /* No LPUART */
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# define STM32_NI2C 2 /* I2C1-2 */
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# define STM32_NCAN 0 /* No CAN */
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# define STM32_NSDIO 0 /* No SDIO */
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# define STM32_NLCD 1 /* LCD 4x44, 8x40 */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NGPIO 83 /* GPIOA-E,H */
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# define STM32_NADC 1 /* ADC1, 24-channels */
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# define STM32_NDAC 2 /* DAC 1, 2 channels */
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# define STM32_NCMP 2 /* (2) Comparators */
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# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */
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# define STM32_NCRC 0 /* No CRC */
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# define STM32_NETHERNET 0 /* No Ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32L152CC)
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# define STM32_NFSMC 0 /* No FSMC */
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# define STM32_NATIM 0 /* No advanced timers */
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# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */
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# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
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# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
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# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */
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# define STM32_NSPI 3 /* SPI1-3 */
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# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */
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# define STM32_NUSART 3 /* USART1-3 */
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# define STM32_NLPUART 0 /* No LPUART */
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# define STM32_NI2C 2 /* I2C1-2 */
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# define STM32_NCAN 0 /* No CAN */
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# define STM32_NSDIO 0 /* No SDIO */
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# define STM32_NLCD 1 /* LCD 4x18 */
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# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NGPIO 37 /* GPIOA-E,H */
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# define STM32_NADC 1 /* ADC1, 14-channels */
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# define STM32_NDAC 2 /* DAC 1, 2 channels */
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# define STM32_NCMP 2 /* (2) Comparators */
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# define STM32_NCAPSENSE 16 /* Capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NETHERNET 0 /* No ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32L152RC)
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# define STM32_NFSMC 0 /* No FSMC */
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# define STM32_NATIM 0 /* No advanced timers */
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# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */
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# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
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# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
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# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */
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# define STM32_NSPI 3 /* SPI1-3 */
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# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */
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# define STM32_NUSART 3 /* USART1-3 */
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# define STM32_NLPUART 0 /* No LPUART */
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# define STM32_NI2C 2 /* I2C1-2 */
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# define STM32_NCAN 0 /* No CAN */
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# define STM32_NSDIO 0 /* No SDIO */
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# define STM32_NLCD 1 /* LCD 4x32, 8x28 */
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# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NGPIO 51 /* GPIOA-E,H */
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# define STM32_NADC 1 /* ADC1, 21-channels */
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# define STM32_NDAC 2 /* DAC 1, 2 channels */
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# define STM32_NCMP 2 /* (2) Comparators */
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# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NETHERNET 0 /* No ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32L152VC)
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# define STM32_NFSMC 0 /* No FSMC */
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# define STM32_NATIM 0 /* No advanced timers */
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# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */
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# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
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# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
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# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */
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# define STM32_NSPI 3 /* SPI1-3 */
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# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */
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# define STM32_NUSART 3 /* USART1-3 */
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# define STM32_NLPUART 0 /* No LPUART */
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# define STM32_NI2C 2 /* I2C1-2 */
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# define STM32_NCAN 0 /* No CAN */
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# define STM32_NSDIO 0 /* No SDIO */
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# define STM32_NLCD 1 /* LCD 4x44, 8x40 */
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# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NGPIO 83 /* GPIOA-E,H */
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# define STM32_NADC 1 /* ADC1, 25-channels */
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# define STM32_NDAC 2 /* DAC 1, 2 channels */
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# define STM32_NCMP 2 /* (2) Comparators */
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# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NETHERNET 0 /* No ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32L151RE) || defined(CONFIG_ARCH_CHIP_STM32L152RE)
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# define STM32_NFSMC 0 /* No FSMC */
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# define STM32_NATIM 0 /* No advanced timers */
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# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */
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# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
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# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
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# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */
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# define STM32_NSPI 3 /* SPI1-3 */
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# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */
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# define STM32_NUSART 5 /* USART1-5 */
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# define STM32_NLPUART 0 /* No LPUART */
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# define STM32_NI2C 2 /* I2C1-2 */
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# define STM32_NCAN 0 /* No CAN */
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# define STM32_NSDIO 0 /* No SDIO */
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# define STM32_NLCD 1 /* LCD 4x44, 8x40 */
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# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NGPIO 51 /* GPIOA-E,H */
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# define STM32_NADC 1 /* ADC1, 25-channels */
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# define STM32_NDAC 2 /* DAC 1, 2 channels */
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# define STM32_NCMP 2 /* (2) Comparators */
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# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NETHERNET 0 /* No ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32L151VE) || defined(CONFIG_ARCH_CHIP_STM32L152VE)
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# define STM32_NFSMC 0 /* No FSMC */
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# define STM32_NATIM 0 /* No advanced timers */
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# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */
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# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
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# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
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# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */
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# define STM32_NSPI 3 /* SPI1-3 */
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# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */
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# define STM32_NUSART 5 /* USART1-5 */
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# define STM32_NLPUART 0 /* No LPUART */
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# define STM32_NI2C 2 /* I2C1-2 */
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# define STM32_NCAN 0 /* No CAN */
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# define STM32_NSDIO 0 /* No SDIO */
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# define STM32_NLCD 1 /* LCD 4x44, 8x40 */
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# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NGPIO 83 /* GPIOA-E,H */
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# define STM32_NADC 1 /* ADC1, 25-channels */
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# define STM32_NDAC 2 /* DAC 1, 2 channels */
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# define STM32_NCMP 2 /* (2) Comparators */
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# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NETHERNET 0 /* No ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32L151QE) || defined(CONFIG_ARCH_CHIP_STM32L152QE)
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# define STM32_NFSMC 0 /* No FSMC */
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# define STM32_NATIM 0 /* No advanced timers */
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# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */
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# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
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# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
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# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */
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# define STM32_NSPI 3 /* SPI1-3 */
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# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */
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# define STM32_NUSART 5 /* USART1-5 */
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# define STM32_NLPUART 0 /* No LPUART */
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# define STM32_NI2C 2 /* I2C1-2 */
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# define STM32_NCAN 0 /* No CAN */
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# define STM32_NSDIO 0 /* No SDIO */
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# define STM32_NLCD 1 /* LCD 4x44, 8x40 */
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# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NGPIO 109 /* GPIOA-E,H */
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# define STM32_NADC 1 /* ADC1, 25-channels */
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# define STM32_NDAC 2 /* DAC 1, 2 channels */
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# define STM32_NCMP 2 /* (2) Comparators */
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# define STM32_NCAPSENSE 33 /* Capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NETHERNET 0 /* No ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32L151ZE) || defined(CONFIG_ARCH_CHIP_STM32L152ZE)
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# define STM32_NFSMC 0 /* No FSMC */
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# define STM32_NATIM 0 /* No advanced timers */
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# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */
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# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
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# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
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# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */
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# define STM32_NSPI 3 /* SPI1-3 */
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# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */
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# define STM32_NUSART 5 /* USART1-5 */
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# define STM32_NLPUART 0 /* No LPUART */
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# define STM32_NI2C 2 /* I2C1-2 */
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# define STM32_NCAN 0 /* No CAN */
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# define STM32_NSDIO 0 /* No SDIO */
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# define STM32_NLCD 1 /* LCD 4x44, 8x40 */
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# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NGPIO 115 /* GPIOA-E,H */
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# define STM32_NADC 1 /* ADC1, 25-channels */
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# define STM32_NDAC 2 /* DAC 1, 2 channels */
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# define STM32_NCMP 2 /* (2) Comparators */
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# define STM32_NCAPSENSE 34 /* Capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NETHERNET 0 /* No ethernet */
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|
# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32L162ZD)
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# define STM32_NFSMC 1 /* FSMC */
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# define STM32_NATIM 0 /* No advanced timers */
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# define STM32_NGTIM 4 /* 16-bit general timers TIM2-4 with DMA
|
|
* 32-bit general timer TIM5 with DMA */
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# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
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|
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 without DMA */
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# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */
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# define STM32_NSPI 3 /* SPI1-3 */
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# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */
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# define STM32_NUSART 5 /* USART1-3, UART4-5 */
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# define STM32_NLPUART 0 /* No LPUART */
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|
# define STM32_NI2C 2 /* I2C1-2 */
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|
# define STM32_NCAN 0 /* No CAN */
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|
# define STM32_NSDIO 1 /* SDIO */
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|
# define STM32_NLCD 1 /* LCD 4x44, 8x40 */
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|
# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */
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|
# define STM32_NGPIO 115 /* GPIOA-G,H */
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# define STM32_NADC 1 /* ADC1, 40-channels */
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|
# define STM32_NDAC 2 /* DAC 1, 2 channels */
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|
# define STM32_NCMP 2 /* (2) Comparators */
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|
# define STM32_NCAPSENSE 34 /* Capacitive sensing channels */
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|
# define STM32_NCRC 1 /* CRC */
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|
# define STM32_NETHERNET 0 /* No ethernet */
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|
# define STM32_NRNG 0 /* No random number generator (RNG) */
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|
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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|
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|
#elif defined(CONFIG_ARCH_CHIP_STM32L162VE)
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|
# define STM32_NFSMC 0 /* No FSMC */
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|
# define STM32_NATIM 0 /* No advanced timers */
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|
# define STM32_NGTIM 4 /* 16-bit general timers TIM2-4 with DMA
|
|
* 32-bit general timer TIM5 with DMA */
|
|
# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
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|
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
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|
# define STM32_NDMA 2 /* DMA1, 12-channels */
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|
# define STM32_NSPI 3 /* SPI1-3 */
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|
# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */
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|
# define STM32_NUSART 5 /* USART1-3, UART4-5 */
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|
# define STM32_NLPUART 0 /* No LPUART */
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|
# define STM32_NI2C 2 /* I2C1-2 */
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|
# define STM32_NCAN 0 /* No CAN */
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|
# define STM32_NSDIO 0 /* No SDIO */
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|
# define STM32_NLCD 1 /* LCD 4x44, 8x40*/
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|
# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */
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|
# define STM32_NGPIO 83 /* GPIOA-G,H */
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|
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|
# define STM32_NADC 1 /* ADC1, 25-channels */
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|
# define STM32_NDAC 2 /* DAC 1, 2 channels */
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|
# define STM32_NCMP 2 /* (2) Comparators */
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|
# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */
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|
# define STM32_NCRC 1 /* CRC */
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|
# define STM32_NETHERNET 0 /* No ethernet */
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|
# define STM32_NRNG 0 /* No random number generator (RNG) */
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|
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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|
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|
/* STM32 F100 Value Line ****************************************************/
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|
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#else
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|
# error "Unsupported STM32 chip"
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|
#endif
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|
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|
/* Peripheral IP versions ***************************************************/
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|
|
|
/* Peripheral IP versions are invariant and should be decided here, not in
|
|
* Kconfig.
|
|
*
|
|
* REVISIT: Currently only SPI IP version is handled here, with others being
|
|
* handled in Kconfig. Those others need to be gradually refactored
|
|
* and resolved here.
|
|
*/
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|
|
|
#define STM32_HAVE_IP_SPI_V1
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|
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|
/* NVIC priority levels *****************************************************/
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|
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|
#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */
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|
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
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|
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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|
#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */
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|
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|
#endif /* __ARCH_ARM_INCLUDE_STM32L1_CHIP_H */
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