mirror of
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ebdd79abd2
BREAKING CHANGE: Part of splitting the legacy stm32 super-directory; relocates the stm32l0 sources, headers and boards into arch/arm/src/stm32l0, arch/arm/include/stm32l0 and boards/arm/stm32l0. Signed-off-by: raiden00pl <raiden00@railab.me>
371 lines
22 KiB
C
371 lines
22 KiB
C
/****************************************************************************
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* arch/arm/include/stm32l0/chip.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_STM32L0_CHIP_H
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#define __ARCH_ARM_INCLUDE_STM32L0_CHIP_H
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#define ARMV6M_PERIPHERAL_INTERRUPTS 32
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Prototypes
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****************************************************************************/
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/* Get customizations for each supported chip */
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#if defined(CONFIG_ARCH_CHIP_STM32L071K8)
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# define STM32_NATIM 0 /* No advanced timers */
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# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3
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* (with DMA) and TIM21-22 without DMA */
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# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */
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# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
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/* 1 LPTIMER */
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# define STM32_NSPI 1 /* 1 SPI modules SPI1 */
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# define STM32_NI2S 0 /* 0 I2S module */
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# define STM32_NI2C 2 /* 2 I2C */
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# define STM32_NDMA 1 /* 1 DMA1, 7-channels */
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# define STM32_NUSART 3 /* 3 USART modules, USART1-3 */
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/* 1 LPUART */
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# define STM32_NCAN 0 /* 0 CAN controllers */
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# define STM32_NLCD 0 /* 0 LCD */
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# define STM32_NUSBDEV 0 /* 0 USB full-speed device controller */
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# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NCEC 0 /* 0 HDMI-CEC controller */
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# define STM32_NADC 1 /* One 12-bit module */
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# define STM32_NDAC 0 /* 0 DAC channel */
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# define STM32_NCOMP 2 /* 2 Analog Comparators */
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# define STM32_NCRC 0 /* 0 CRC module */
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# define STM32_NRNG 0 /* 0 Random number generator (RNG) */
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# define STM32_NCAP 0 /* 0 Capacitive sensing channels */
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */
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#elif defined(CONFIG_ARCH_CHIP_STM32L053C8)
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# define STM32_NATIM 0 /* No advanced timers */
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# define STM32_NGTIM16 3 /* 16-bit general up/down timers TIM2-3
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* (with DMA) and TIM22 without DMA */
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# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */
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# define STM32_NBTIM 1 /* 1 basic timers: TIM6 with DMA */
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/* 1 LPTIMER */
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# define STM32_NSPI 2 /* 2 SPI modules SPI1 */
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# define STM32_NI2S 1 /* 1 I2S module */
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# define STM32_NI2C 2 /* 2 I2C */
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# define STM32_NDMA 1 /* 1 DMA1, 7-channels */
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# define STM32_NUSART 2 /* 2 USART modules, USART1-1 */
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/* 1 LPUART */
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# define STM32_NCAN 0 /* 0 CAN controllers */
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# define STM32_NLCD 1 /* 1 LCD */
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# define STM32_NUSBDEV 1 /* 1 USB full-speed device controller */
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# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NCEC 0 /* 0 HDMI-CEC controller */
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# define STM32_NADC 1 /* One 12-bit module */
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# define STM32_NDAC 0 /* 0 DAC channel */
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# define STM32_NCOMP 2 /* 2 Analog Comparators */
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# define STM32_NCRC 0 /* 0 CRC module */
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# define STM32_NRNG 0 /* 0 Random number generator (RNG) */
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# define STM32_NCAP 24 /* 24 Capacitive sensing channels */
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */
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#elif defined(CONFIG_ARCH_CHIP_STM32L053R8)
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# define STM32_NATIM 0 /* No advanced timers */
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# define STM32_NGTIM16 3 /* 16-bit general up/down timers TIM2-3
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* (with DMA) and TIM22 without DMA */
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# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */
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# define STM32_NBTIM 1 /* 1 basic timers: TIM6 with DMA */
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/* 1 LPTIMER */
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# define STM32_NSPI 2 /* 2 SPI modules SPI1 */
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# define STM32_NI2S 1 /* 1 I2S module */
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# define STM32_NI2C 2 /* 2 I2C */
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# define STM32_NDMA 1 /* 1 DMA1, 7-channels */
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# define STM32_NUSART 2 /* 2 USART modules, USART1-1 */
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/* 1 LPUART */
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# define STM32_NCAN 0 /* 0 CAN controllers */
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# define STM32_NLCD 1 /* 1 LCD */
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# define STM32_NUSBDEV 1 /* 1 USB full-speed device controller */
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# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NCEC 0 /* 0 HDMI-CEC controller */
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# define STM32_NADC 1 /* One 12-bit module */
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# define STM32_NDAC 0 /* 0 DAC channel */
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# define STM32_NCOMP 2 /* 2 Analog Comparators */
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# define STM32_NCRC 0 /* 0 CRC module */
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# define STM32_NRNG 0 /* 0 Random number generator (RNG) */
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# define STM32_NCAP 24 /* 24 Capacitive sensing channels */
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */
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#elif defined(CONFIG_ARCH_CHIP_STM32L071C8) || defined(CONFIG_ARCH_CHIP_STM32L071V8) || \
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defined(CONFIG_ARCH_CHIP_STM32L071CB) || defined(CONFIG_ARCH_CHIP_STM32L071VB) || \
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defined(CONFIG_ARCH_CHIP_STM32L071RB) || defined(CONFIG_ARCH_CHIP_STM32L071CZ) || \
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defined(CONFIG_ARCH_CHIP_STM32L071VZ) || defined(CONFIG_ARCH_CHIP_STM32L071RZ)
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# define STM32_NATIM 0 /* 0 advanced timers */
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# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3
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* (with DMA) and TIM21-22 without DMA */
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# define STM32_NGTIM32 0 /* 0 32-bit general up/down timers */
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# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
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/* 1 LPTIMER */
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# define STM32_NSPI 2 /* 2 SPI modules SPI1-2 */
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# define STM32_NI2S 1 /* 1 I2S module */
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# define STM32_NI2C 3 /* 3 I2C */
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# define STM32_NDMA 1 /* 1 DMA1, 7-channels */
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# define STM32_NUSART 4 /* 4 USART modules, USART1-4 */
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/* 1 LPUART */
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# define STM32_NCAN 0 /* 0 CAN controllers */
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# define STM32_NLCD 0 /* 0 LCD */
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# define STM32_NUSBDEV 0 /* 0 USB full-speed device controller */
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# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NCEC 0 /* 0 HDMI-CEC controller */
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# define STM32_NADC 1 /* One 12-bit module */
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# define STM32_NDAC 0 /* 0 DAC channel */
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# define STM32_NCOMP 2 /* 2 Analog Comparators */
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# define STM32_NCRC 0 /* 0 CRC module */
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# define STM32_NRNG 0 /* 0 Random number generator (RNG) */
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# define STM32_NCAP 0 /* 0 Capacitive sensing channels */
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */
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#elif defined(CONFIG_ARCH_CHIP_STM32L071KB) || defined(CONFIG_ARCH_CHIP_STM32L071KZ)
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# define STM32_NATIM 0 /* 0 advanced timers */
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# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3
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* (with DMA) and TIM21-22 without DMA */
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# define STM32_NGTIM32 0 /* 0 32-bit general up/down timers */
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# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
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/* 1 LPTIMER */
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# define STM32_NSPI 1 /* 1 SPI modules SPI1 */
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# define STM32_NI2S 0 /* 0 I2S module */
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# define STM32_NI2C 3 /* 3 I2C */
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# define STM32_NDMA 1 /* 1 DMA1, 7-channels */
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# define STM32_NUSART 4 /* 4 USART modules, USART1-4 */
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/* 1 LPUART */
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# define STM32_NCAN 0 /* 0 CAN controllers */
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# define STM32_NLCD 0 /* 0 LCD */
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# define STM32_NUSBDEV 0 /* 0 USB full-speed device controller */
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# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NCEC 0 /* 0 HDMI-CEC controller */
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# define STM32_NADC 1 /* One 12-bit module */
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# define STM32_NDAC 0 /* 0 DAC channel */
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# define STM32_NCOMP 2 /* 2 Analog Comparators */
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# define STM32_NCRC 0 /* 0 CRC module */
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# define STM32_NRNG 0 /* 0 Random number generator (RNG) */
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# define STM32_NCAP 0 /* 0 Capacitive sensing channels */
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */
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#elif defined(CONFIG_ARCH_CHIP_STM32L072V8) || defined(CONFIG_ARCH_CHIP_STM32L072VB) || \
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defined(CONFIG_ARCH_CHIP_STM32L072VZ)
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# define STM32_NATIM 0 /* No advanced timers */
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# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3
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* (with DMA) and TIM21-22 without DMA */
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# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */
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# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */
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/* One LPTIMER */
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# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */
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# define STM32_NI2S 1 /* One I2S module */
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# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */
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# define STM32_NDMA 1 /* One DMA1, 7-channels */
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# define STM32_NUSART 4 /* Four USART modules, USART1-4 */
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/* One LPUART */
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# define STM32_NCAN 0 /* No CAN controllers */
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
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# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NCEC 0 /* No HDMI-CEC controller */
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# define STM32_NADC 1 /* One 12-bit module */
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# define STM32_NDAC 2 /* Two DAC channels */
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# define STM32_NCOMP 2 /* Two Analog Comparators */
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# define STM32_NCRC 1 /* One CRC module */
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# define STM32_NRNG 1 /* One Random number generator (RNG) */
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# define STM32_NCAP 24 /* Twenty-four Capacitive sensing channels */
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */
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#elif defined(CONFIG_ARCH_CHIP_STM32L072KB) || defined(CONFIG_ARCH_CHIP_STM32L072KZ)
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# define STM32_NATIM 0 /* No advanced timers */
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# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3
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* (with DMA) and TIM21-22 without DMA */
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# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */
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# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */
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/* One LPTIMER */
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# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */
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# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */
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# define STM32_NDMA 1 /* One DMA1, 7-channels */
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# define STM32_NUSART 4 /* Four USART modules, USART1-4 */
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/* One LPUART */
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# define STM32_NCAN 0 /* No CAN controllers */
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
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# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NCEC 0 /* No HDMI-CEC controller */
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# define STM32_NADC 1 /* One 12-bit module */
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# define STM32_NDAC 2 /* Two DAC channels */
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# define STM32_NCOMP 2 /* Two Analog Comparators */
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# define STM32_NCRC 1 /* One CRC module */
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# define STM32_NRNG 1 /* One Random number generator (RNG) */
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# define STM32_NCAP 13 /* Thirteen Capacitive sensing channels */
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */
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#elif defined(CONFIG_ARCH_CHIP_STM32L072CB) || defined(CONFIG_ARCH_CHIP_STM32L072CZ)
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# define STM32_NATIM 0 /* No advanced timers */
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# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3
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* (with DMA) and TIM21-22 without DMA */
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# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */
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# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */
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/* One LPTIMER */
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# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */
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# define STM32_NI2S 1 /* One I2S module */
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# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */
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# define STM32_NDMA 1 /* One DMA1, 7-channels */
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# define STM32_NUSART 4 /* Four USART modules, USART1-4 */
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/* One LPUART */
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# define STM32_NCAN 0 /* No CAN controllers */
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
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# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NCEC 0 /* No HDMI-CEC controller */
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# define STM32_NADC 1 /* One 12-bit module */
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# define STM32_NDAC 2 /* Two DAC channels */
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# define STM32_NCOMP 2 /* Two Analog Comparators */
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# define STM32_NCRC 1 /* One CRC module */
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# define STM32_NRNG 1 /* One Random number generator (RNG) */
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# define STM32_NCAP 18 /* Nineteen Capacitive sensing channels */
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */
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#elif defined(CONFIG_ARCH_CHIP_STM32L072RB) || defined(CONFIG_ARCH_CHIP_STM32L072RZ)
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# define STM32_NATIM 0 /* No advanced timers */
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# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3
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* (with DMA) and TIM21-22 without DMA */
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# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */
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# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */
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/* One LPTIMER */
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# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */
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# define STM32_NI2S 1 /* One I2S module */
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# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */
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# define STM32_NDMA 1 /* One DMA1, 7-channels */
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# define STM32_NUSART 4 /* Four USART modules, USART1-4 */
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/* One LPUART */
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# define STM32_NCAN 0 /* No CAN controllers */
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
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# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NCEC 0 /* No HDMI-CEC controller */
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# define STM32_NADC 1 /* One 12-bit module */
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# define STM32_NDAC 2 /* Two DAC channels */
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# define STM32_NCOMP 2 /* Two Analog Comparators */
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# define STM32_NCRC 1 /* One CRC module */
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# define STM32_NRNG 1 /* One Random number generator (RNG) */
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# define STM32_NCAP 24 /* Twenty-four Capacitive sensing channels */
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */
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#elif defined(CONFIG_ARCH_CHIP_STM32L073V8) || defined(CONFIG_ARCH_CHIP_STM32L073VB) || \
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defined(CONFIG_ARCH_CHIP_STM32L073VZ)
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# define STM32_NATIM 0 /* No advanced timers */
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# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3
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* (with DMA) and TIM21-22 without DMA */
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# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */
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# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */
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/* One LPTIMER */
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# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */
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# define STM32_NI2S 1 /* One I2S module */
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# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */
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# define STM32_NDMA 1 /* One DMA1, 7-channels */
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# define STM32_NUSART 4 /* Four USART modules, USART1-4 */
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/* One LPUART */
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# define STM32_NCAN 0 /* No CAN controllers */
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# define STM32_NLCD 1 /* One LCD controller */
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# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
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# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NCEC 0 /* No HDMI-CEC controller */
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# define STM32_NADC 1 /* One 12-bit module */
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# define STM32_NDAC 2 /* Two DAC channels */
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# define STM32_NCOMP 2 /* Two Analog Comparators */
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# define STM32_NCRC 1 /* One CRC module */
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# define STM32_NRNG 1 /* One Random number generator (RNG) */
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# define STM32_NCAP 24 /* Twenty-four Capacitive sensing channels */
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */
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#elif defined(CONFIG_ARCH_CHIP_STM32L073CB) || defined(CONFIG_ARCH_CHIP_STM32L073CZ)
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# define STM32_NATIM 0 /* No advanced timers */
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# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3
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* (with DMA) and TIM21-22 without DMA */
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# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */
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# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */
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/* One LPTIMER */
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# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */
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# define STM32_NI2S 1 /* One I2S module */
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# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */
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# define STM32_NDMA 1 /* One DMA1, 7-channels */
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# define STM32_NUSART 4 /* Four USART modules, USART1-4 */
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/* One LPUART */
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# define STM32_NCAN 0 /* No CAN controllers */
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# define STM32_NLCD 1 /* One LCD controller */
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# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
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# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NCEC 0 /* No HDMI-CEC controller */
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# define STM32_NADC 1 /* One 12-bit module */
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# define STM32_NDAC 2 /* Two DAC channels */
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# define STM32_NCOMP 2 /* Two Analog Comparators */
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# define STM32_NCRC 1 /* One CRC module */
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# define STM32_NRNG 1 /* One Random number generator (RNG) */
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# define STM32_NCAP 17 /* Seventeen Capacitive sensing channels */
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */
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#elif defined(CONFIG_ARCH_CHIP_STM32L073RB) || defined(CONFIG_ARCH_CHIP_STM32L073RZ)
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# define STM32_NATIM 0 /* No advanced timers */
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# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3
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* (with DMA) and TIM21-22 without DMA */
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# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */
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# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */
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/* One LPTIMER */
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# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */
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# define STM32_NI2S 1 /* One I2S module */
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# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */
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# define STM32_NDMA 1 /* One DMA1, 7-channels */
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# define STM32_NUSART 4 /* Four USART modules, USART1-4 */
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/* One LPUART */
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# define STM32_NCAN 0 /* No CAN controllers */
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# define STM32_NLCD 1 /* One LCD controller */
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# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
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# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NCEC 0 /* No HDMI-CEC controller */
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# define STM32_NADC 1 /* One 12-bit module */
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# define STM32_NDAC 2 /* Two DAC channels */
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# define STM32_NCOMP 2 /* Two Analog Comparators */
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# define STM32_NCRC 1 /* One CRC module */
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# define STM32_NRNG 1 /* One Random number generator (RNG) */
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# define STM32_NCAP 24 /* Twenty-four Capacitive sensing channels */
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */
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#endif
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/* NVIC priority levels *****************************************************/
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/* Each priority field holds a priority value, 0-31. The lower the value,
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* the greater the priority of the corresponding interrupt. The processor
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* implements only bits[7:6] of each field, bits[5:0] read as zero and
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* ignore writes.
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*/
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#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */
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#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
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#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt priority used */
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#endif /* __ARCH_ARM_INCLUDE_STM32L0_CHIP_H */
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