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BREAKING CHANGE: Part of splitting the legacy stm32 super-directory; relocates the stm32g0 sources, headers and boards into arch/arm/src/stm32g0, arch/arm/include/stm32g0 and boards/arm/stm32g0. Signed-off-by: raiden00pl <raiden00@railab.me>
166 lines
8.4 KiB
C
166 lines
8.4 KiB
C
/****************************************************************************
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* arch/arm/include/stm32g0/chip.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_STM32G0_CHIP_H
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#define __ARCH_ARM_INCLUDE_STM32G0_CHIP_H
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#define ARMV6M_PERIPHERAL_INTERRUPTS 32
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Prototypes
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****************************************************************************/
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/* Get customizations for each supported chip */
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#if defined(CONFIG_ARCH_CHIP_STM32G070KB) || defined(CONFIG_ARCH_CHIP_STM32G070CB) || \
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defined(CONFIG_ARCH_CHIP_STM32G070RB)
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# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */
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# define STM32_SRAM_SIZE (32 * 1024) /* 32Kb */
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# define STM32_NATIM 1 /* One advanced timer TIM1 */
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# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3,
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* TIM14-17 */
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# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */
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# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 */
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# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */
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# define STM32_NI2S 1 /* One I2S module (SPI or I2S) */
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# define STM32_NI2C 2 /* Two I2C (1 with SMBus/PMBus) */
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# define STM32_NDMA 1 /* One DMA1, 7-channels */
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# define STM32_NUSART 4 /* Four USART modules, USART1-4 */
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# define STM32_NCAN 0 /* No CAN controllers */
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
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# define STM32_NUSBOTG 0 /* No USB OTG */
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# define STM32_NCEC 0 /* One HDMI-CEC controller */
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# define STM32_NADC 1 /* (1) ADC1, 16-channels */
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# define STM32_NDAC 0 /* No DAC */
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# define STM32_NCOMP 0 /* No Analog Comparators */
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# define STM32_NCRC 1 /* No CRC module */
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# define STM32_NRNG 0 /* No Random number generator (RNG) */
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# define STM32_NCAP 0 /* No Capacitive sensing channels */
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
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#elif defined(CONFIG_ARCH_CHIP_STM32G071EB) || defined(CONFIG_ARCH_CHIP_STM32G071G8) || \
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defined(CONFIG_ARCH_CHIP_STM32G071GB) || defined(CONFIG_ARCH_CHIP_STM32G071G8XN) || \
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defined(CONFIG_ARCH_CHIP_STM32G071GBXN) || defined(CONFIG_ARCH_CHIP_STM32G071K8) || \
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defined(CONFIG_ARCH_CHIP_STM32G071KB) || defined(CONFIG_ARCH_CHIP_STM32G071K8XN) || \
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defined(CONFIG_ARCH_CHIP_STM32G071KBXN) || defined(CONFIG_ARCH_CHIP_STM32G071C8) || \
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defined(CONFIG_ARCH_CHIP_STM32G071CB) || defined(CONFIG_ARCH_CHIP_STM32G071R8) || \
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defined(CONFIG_ARCH_CHIP_STM32G071RB)
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# define STM32_NATIM 1 /* One advanced timer TIM1 */
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# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3
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* (with DMA) and TIM21-22 without DMA */
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# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */
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# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */
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/* Two LPTIMER */
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# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */
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# define STM32_NI2C 2 /* Two I2C (2 with SMBus/PMBus) */
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# define STM32_NDMA 1 /* One DMA1, 7-channels */
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# define STM32_NUSART 4 /* Four USART modules, USART1-4 */
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/* One LPUART */
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# define STM32_NCAN 0 /* No CAN controllers */
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
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# define STM32_NUSBOTG 0 /* No USB OTG */
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# define STM32_NCEC 1 /* One HDMI-CEC controller */
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# define STM32_NADC 1 /* (1) ADC1, 12-channels */
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# define STM32_NDAC 2 /* Two DAC channels */
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# define STM32_NCOMP 2 /* Two Analog Comparators */
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# define STM32_NCRC 0 /* No CRC module */
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# define STM32_NRNG 0 /* No Random number generator (RNG) */
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# define STM32_NCAP 0 /* No Capacitive sensing channels */
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
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#elif defined(CONFIG_ARCH_CHIP_STM32G0B1KB) || defined(CONFIG_ARCH_CHIP_STM32G0B1CB) || \
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defined(CONFIG_ARCH_CHIP_STM32G0B1RB) || defined(CONFIG_ARCH_CHIP_STM32G0B1MB) || \
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defined(CONFIG_ARCH_CHIP_STM32G0B1VB) || defined(CONFIG_ARCH_CHIP_STM32G0B1KC) || \
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defined(CONFIG_ARCH_CHIP_STM32G0B1CC) || defined(CONFIG_ARCH_CHIP_STM32G0B1RC) || \
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defined(CONFIG_ARCH_CHIP_STM32G0B1MC) || defined(CONFIG_ARCH_CHIP_STM32G0B1VC) || \
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defined(CONFIG_ARCH_CHIP_STM32G0B1KE) || defined(CONFIG_ARCH_CHIP_STM32G0B1CE) || \
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defined(CONFIG_ARCH_CHIP_STM32G0B1RE) || defined(CONFIG_ARCH_CHIP_STM32G0B1NE) || \
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defined(CONFIG_ARCH_CHIP_STM32G0B1ME) || defined(CONFIG_ARCH_CHIP_STM32G0B1VE)
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# define STM32_NATIM 1 /* One advanced timer TIM1 */
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# define STM32_NGTIM16 6 /* 16-bit general purpose timers */
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# define STM32_NGTIM32 1 /* TIM2 */
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# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */
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/* One LPTIMER */
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# define STM32_NSPI 3 /* Two SPI modules SPI1-2 */
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# define STM32_NI2C 3 /* Two I2C (2 with SMBus/PMBus) */
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# define STM32_NDMA 2 /* DMA1 7-channels, DMA2 5-channels DMA1 */
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# define STM32_NUSART 6 /* Six USART modules, USART1-6 */
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/* Two LPUART */
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# define STM32_NCAN 1 /* One FDCAN controller */
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBDEV 1 /* One USB full-speed controller */
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# define STM32_NUSBOTG 0 /* No USB OTG */
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# define STM32_NCEC 1 /* One HDMI-CEC controller */
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# define STM32_NADC 1 /* (1) ADC1, 12-channels */
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# define STM32_NDAC 2 /* Two DAC channels */
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# define STM32_NCOMP 3 /* Three Analog Comparators */
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# define STM32_NCRC 0 /* No CRC module */
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# define STM32_NRNG 1 /* One Random number generator (RNG) */
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# define STM32_NCAP 0 /* No Capacitive sensing channels */
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
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/* STM32L EnergyLite Line ***************************************************/
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/* STM32L073XX - With LCD
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* STM32L072XX - No LCD
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* STM32L071XX - Access line, no LCD
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*
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* STM32L0XXX8 - 64KB FLASH, 20KB SRAM, 3KB EEPROM
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* STM32L0XXXB - 128KB FLASH, 20KB SRAM, 6KB EEPROM
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* STM32L0XXXZ - 192KB FLASH, 20KB SRAM, 3KB EEPROM
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*
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* STM32L0XXCX - 48-pins
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* STM32L0XXRX - 64-pins
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* STM32L0XXVX - 100-pins
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*/
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#endif
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/* NVIC priority levels *****************************************************/
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/* Each priority field holds a priority value, 0-31. The lower the value,
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* the greater the priority of the corresponding interrupt. The processor
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* implements only bits[7:6] of each field, bits[5:0] read as zero and
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* ignore writes.
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*/
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#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */
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#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
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#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt priority used */
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#endif /* __ARCH_ARM_INCLUDE_STM32G0_CHIP_H */
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