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d523171d01
Add intiial support for STM32C562 and use common STM32 M33 sources. Signed-off-by: raiden00pl <raiden00@railab.me> Assisted-by: Claude Code
80 lines
3.5 KiB
C
80 lines
3.5 KiB
C
/****************************************************************************
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* arch/arm/include/stm32c5/chip.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_STM32C5_CHIP_H
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#define __ARCH_ARM_INCLUDE_STM32C5_CHIP_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define STM32_SRAM1_SIZE 0x00010000 /* 64 KiB SRAM1 */
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#define STM32_SRAM2_SIZE 0x00010000 /* 64 KiB SRAM2 */
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/* SRAM1 and SRAM2 are contiguous on STM32C5. */
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#define STM32_PRIMARY_SRAM_SIZE 0x00020000
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#define STM32_NFSMC 0 /* No external memory controller */
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#define STM32_NATIM 2 /* TIM1 and TIM8 */
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#define STM32_NGTIM32 2 /* TIM2 and TIM5 */
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#define STM32_NGTIM16 1 /* TIM12 */
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#define STM32_NGTIMNDMA 3 /* TIM15, TIM16 and TIM17 */
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#define STM32_NBTIM 2 /* TIM6 and TIM7 */
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#define STM32_NLPTIM 1 /* LPTIM1 */
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#define STM32_NRNG 1 /* Random number generator */
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#define STM32_NUART 2 /* UART4 and UART5 */
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#define STM32_NUSART 3 /* USART1, USART2 and USART3 */
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#define STM32_NLPUART 1 /* LPUART1 */
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#define STM32_QSPI 0 /* No QuadSPI controller */
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#define STM32_OCTOSPI 0 /* No OctoSPI controller */
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#define STM32_NSPI 3 /* SPI1 through SPI3 */
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#define STM32_NI2C 2 /* I2C1 and I2C2 */
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#define STM32_NI3C 1 /* I3C1 */
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#define STM32_NSWPMI 0 /* No SWPMI controller */
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#define STM32_NUSBOTGFS 1 /* USB device/host full speed */
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#define STM32_NUSBFS 0 /* No USB device-only controller */
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#define STM32_NCAN 1 /* FDCAN1 */
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#define STM32_NSAI 0 /* No SAI controller */
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#define STM32_NSDMMC 0 /* No SDMMC controller */
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#define STM32_NDMA 2 /* LPDMA1 and LPDMA2 */
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#define STM32_NPORTS 8 /* GPIOA-E and GPIOH */
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#define STM32_NADC 2 /* ADC1 and ADC2 */
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#define STM32_NDAC 1 /* DAC1 */
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#define STM32_NCRC 1 /* CRC */
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#define STM32_NCOMP 1 /* COMP1 */
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#define STM32_NOPAMP 0 /* No operational amplifier */
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/* NVIC priority levels */
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#define NVIC_SYSH_PRIORITY_MIN 0xf0
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#define NVIC_SYSH_PRIORITY_DEFAULT 0x80
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#define NVIC_SYSH_PRIORITY_MAX 0x00
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#define NVIC_SYSH_PRIORITY_STEP 0x10
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#endif /* __ARCH_ARM_INCLUDE_STM32C5_CHIP_H */
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