nuttx/boards/xtensa
Felipe Moura e4cc7b7258 boards/esp32s3: the LSM6DS3TR-C INT1 is a level, not an edge
The FIFO watermark flag is a level: it stays high until the worker
actually drains the FIFO below the threshold.  Configuring INT1 as RISING
made that a race the driver could lose permanently.

lsm6ds3trc_interrupt() disables its IRQ on entry and re-enables it after
the worker has run.  With an edge trigger, if the line is still high when
the IRQ is re-enabled -- which is precisely what happens whenever a drain
does not take the FIFO below the watermark -- there is no new low-to-high
transition left to detect, and the line goes mute forever.  Observed as a
board that serviced exactly one watermark after boot and then never
again, reproducible 2 out of 2 reflashes.

ONHIGH matches the physical meaning of the pin and is immune to it: a
level trigger re-asserts on its own for as long as the condition holds,
and the disable/enable pairing around servicing is what stops that from
live-locking.

Validated with more than 900 consecutive drains (~100 min) including real
sleep -> GPIO-wake -> resume transitions, the exact case that used to
wedge.

Signed-off-by: Felipe Moura <moura.fmo@gmail.com>
Assisted-by: Claude:claude-opus-5
2026-09-22 09:21:08 -03:00
..
esp32 arch, boards, cmake: Build C++ ELF modules without __cxa_atexit. 2026-09-04 15:44:24 -03:00
esp32s2 !arch/arm: Use r9 as the PIC base register. 2026-08-06 01:38:23 +08:00
esp32s3 boards/esp32s3: the LSM6DS3TR-C INT1 is a level, not an edge 2026-09-22 09:21:08 -03:00