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385b945ea9
Give the QEMU boards the same directly addressable media the sim configuration has: rammtd answers BIOC_XIPBASE with the base of its buffer, so xipfs layered on it hands out real pointers and the in-place mmap path can be exercised on an ARM target with no flash present. Registered as /dev/rammtd and mounted at /mnt/xipfs when xipfs is configured. Both mps2-an500 (Cortex-M7, armv7e-m) and mps2-an521 (Cortex-M33, armv8-m) get it, which is what makes the filesystem testable on two different core generations without either one needing flash. Each board also gets a xipfs configuration that runs the test suite, so the bringup above is exercised rather than only compiled. Both run the suite to completion under QEMU 10.1, 90 checks apiece, the power loss sweeps included. The an521 configuration carries CONFIG_CMSDK_UART0_RX_IRQ=48 and _TX_IRQ=49 rather than the reversed pair the an521 nsh configuration uses. That is the SSE-200 order, receive first, and the one consistent both with the overflow interrupt at 63 that nsh already has and with mps2-an500, which puts RX at 16 and TX at 17. With the pair reversed the TX interrupt reaches uart_cmsdk_rx_interrupt, which acknowledges only UART_INTSTATUS_RX, so the board live-locks on its first console write. Correcting nsh is left to a separate change. Assisted-by: Claude Code:claude-opus-5 Signed-off-by: Marco Casaroli <marco.casaroli@gmail.com>
88 lines
2.2 KiB
Text
88 lines
2.2 KiB
Text
#
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# This file is autogenerated: PLEASE DO NOT EDIT IT.
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#
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# You can use "make menuconfig" to make any modifications to the installed .config file.
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# You can then do "make savedefconfig" to generate a new defconfig file that includes your
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# modifications.
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#
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CONFIG_ARCH="arm"
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CONFIG_ARCH_BOARD="mps2-an500"
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CONFIG_ARCH_BOARD_MPS2_AN500=y
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CONFIG_ARCH_CHIP="mps"
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CONFIG_ARCH_CHIP_MPS2_AN500=y
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CONFIG_ARCH_CHIP_MPS=y
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CONFIG_ARCH_INTERRUPTSTACK=2048
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CONFIG_ARCH_STACKDUMP=y
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CONFIG_ARMV7M_SYSTICK=y
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CONFIG_ARM_MPU=y
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CONFIG_ARM_MPU_NREGIONS=1
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CONFIG_ARM_MPU_RESET=y
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CONFIG_BUILTIN=y
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CONFIG_CMSDK_UART0=y
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CONFIG_CMSDK_UART0_BASE=0x40004000
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CONFIG_CMSDK_UART0_CLOCK=25000000
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CONFIG_CMSDK_UART0_OV_IRQ=28
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CONFIG_CMSDK_UART0_RX_IRQ=16
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CONFIG_CMSDK_UART0_SERIAL_CONSOLE=y
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CONFIG_CMSDK_UART0_TX_IRQ=17
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CONFIG_CMSDK_UART=y
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CONFIG_CXX_STANDARD="c++17"
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CONFIG_DEBUG_ASSERTIONS=y
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CONFIG_DEBUG_BUSFAULT=y
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CONFIG_DEBUG_FEATURES=y
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CONFIG_DEBUG_HARDFAULT_ALERT=y
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CONFIG_DEBUG_SCHED=y
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CONFIG_DEBUG_SCHED_ERROR=y
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CONFIG_DEBUG_SCHED_INFO=y
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CONFIG_DEBUG_SCHED_WARN=y
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CONFIG_DEBUG_SYMBOLS=y
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CONFIG_DEBUG_USAGEFAULT=y
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CONFIG_DEFAULT_TASK_STACKSIZE=4096
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CONFIG_EXPERIMENTAL=y
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CONFIG_FRAME_POINTER=y
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CONFIG_FS_PROCFS=y
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CONFIG_FS_ROMFS=y
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CONFIG_FS_TMPFS=y
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CONFIG_FS_XIPFS=y
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CONFIG_FS_XIPFS_FAULT_INJECT=y
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CONFIG_HAVE_CXX=y
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CONFIG_HAVE_CXXINITIALIZE=y
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CONFIG_IDLETHREAD_STACKSIZE=4096
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CONFIG_INIT_ENTRYPOINT="nsh_main"
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CONFIG_INTELHEX_BINARY=y
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CONFIG_LIBC_MEMFD_ERROR=y
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CONFIG_LIBC_STRERROR=y
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CONFIG_LIBC_STRERROR_ERRNUM=y
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CONFIG_MTD=y
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CONFIG_NSH_BUILTIN_APPS=y
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CONFIG_NSH_FILEIOSIZE=512
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CONFIG_NSH_READLINE=y
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CONFIG_PREALLOC_TIMERS=4
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CONFIG_PROFILE_ALL=y
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CONFIG_PROFILE_MINI=y
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CONFIG_RAMLOG=y
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CONFIG_RAMMTD=y
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CONFIG_RAMMTD_FLASHSIM=y
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CONFIG_RAM_SIZE=2097152
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CONFIG_RAM_START=0x60000000
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CONFIG_RAW_BINARY=y
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CONFIG_READLINE_CMD_HISTORY=y
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CONFIG_RR_INTERVAL=200
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CONFIG_SCHED_HPWORK=y
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CONFIG_SCHED_HPWORKPRIORITY=192
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CONFIG_SCHED_IRQMONITOR=y
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CONFIG_SPINLOCK=y
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CONFIG_STACK_COLORATION=y
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CONFIG_STANDARD_SERIAL=y
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CONFIG_START_DAY=25
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CONFIG_START_MONTH=4
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CONFIG_START_YEAR=2023
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CONFIG_SYMTAB_ORDEREDBYNAME=y
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CONFIG_SYSTEM_GPROF=y
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CONFIG_SYSTEM_NSH=y
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CONFIG_SYSTEM_SYSTEM=y
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CONFIG_SYSTEM_XIPFS=y
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CONFIG_TESTING_FS_XIPFS=y
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CONFIG_TIMER=y
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CONFIG_TIMER_ARCH=y
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CONFIG_USEC_PER_TICK=1000
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