hujun5 2a08860a08 arch/arm64: fix backtrace register access and gdbstub config guard ... Fix arm64_backtrace to access TCB register context directly instead of using running_regs(), which may not reflect the actual context being backtraced. Add CONFIG_ARCH_HAVE_DEBUG guard to prevent undefined references in non-debug builds. Signed-off-by: hujun5 <hujun5@xiaomi.com>		2026-01-16 08:55:47 -03:00
..
arm	ghs: fix the UsageFault:INVSTATE error triggered by exception_common	2026-01-16 09:41:13 +08:00
arm64	arch/arm64: fix backtrace register access and gdbstub config guard	2026-01-16 08:55:47 -03:00
avr	nuttx/arch: merge tickless and tick process	2026-01-12 16:20:42 +08:00
ceva	barrier: add UP_RMB UP_WMB	2025-12-22 10:22:06 -03:00
dummy
hc	arch/udelay: Make common, weak definition of up_*delay functions	2025-09-29 09:22:56 +08:00
mips	sched:use tcb_s inside of task_tcb_s , remove all cast	2025-12-22 17:55:45 +08:00
misoc	arch/Toolchain.defs: use _start entry	2025-12-16 13:07:37 -03:00
or1k	arch/Toolchain.defs: use _start entry	2025-12-16 13:07:37 -03:00
renesas	renesas/rx65n: Replace spinlock/sched_lock with spin_lock_irqsave_nopreempt	2025-11-04 22:46:15 +08:00
risc-v	nuttx/arch: merge tickless and tick process	2026-01-12 16:20:42 +08:00
sim	sim/usrsock: move g_work_queue init before net_initialize	2026-01-16 09:39:02 +08:00
sparc	nuttx/arch: merge tickless and tick process	2026-01-12 16:20:42 +08:00
tricore	arch/tricore: record trapinfo for coredump	2026-01-15 16:09:13 -03:00
x86	arch/Toolchain.defs: use _start entry	2025-12-16 13:07:37 -03:00
x86_64	arch/x64:Fix the abnormal backtrace display issue	2026-01-16 09:38:09 +08:00
xtensa	nuttx/arch: merge tickless and tick process	2026-01-12 16:20:42 +08:00
z16	arch/udelay: Make common, weak definition of up_*delay functions	2025-09-29 09:22:56 +08:00
z80	arch/Toolchain.defs: use _start entry	2025-12-16 13:07:37 -03:00
CMakeLists.txt
Kconfig	arch/tricore: upcsa/lowcsa process && dumpinfo	2026-01-15 16:09:13 -03:00