Lwazi Dube 25aa695a35 Reviewed by David Sidrane. ... boards/arm/stm32h7/stm32h747i-disco: Remove references to nucleo in the stm32h747i-disco board. arch/arm/include/stm32h7, arch/arm/src/stm32h7, and boards/arm/stm32h7/stm32h747i-disco: Add support for the STM32H747I-DISCO board.		2019-11-18 14:03:38 -06:00
..
a1x
am335x	arch/arm/include/amm335x: Trivial, cosmetic changes after review	2019-01-08 08:15:04 -06:00
arm	Squashed commit of the following:	2019-04-29 14:52:05 -06:00
armv6-m	Squashed commit of the following:	2019-04-29 14:52:05 -06:00
armv7-a	Squashed commit of the following:	2019-04-29 14:52:05 -06:00
armv7-m	This commit removes CONFIG_ARCH_INT_DISABLEALL. In the normal course of things, interrupts must occasionally be disabled using the up_irq_save() inline function to prevent contention in use of resources that may be shared between interrupt level and non-interrupt level logic. Now the question arises, if we are using BASEPRI to disable interrupts and have high priority interrupts enabled (CONFIG_ARCH_HIPRI_INTERRUPT=y), do we disable all interrupts except SVCall (we cannot disable SVCall interrupts). Or do we only disable the "normal" interrupts?	2019-08-09 10:52:35 -06:00
armv7-r	Squashed commit of the following:	2019-04-29 14:52:05 -06:00
c5471
cxd56xx	Merged in alinjerpelea/nuttx (pull request #1061)	2019-10-24 14:26:02 +00:00
dm320
efm32	In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.	2018-12-03 17:41:59 -06:00
imx1
imx6	Fix lots of typos in C comments and Kconfig help text	2018-07-08 18:24:45 -06:00
imxrt	Merged imxrt1020 into master	2019-04-30 16:08:46 -06:00
kinetis	Merged in dagar/nuttx/pr-kinetic_minor_fix (pull request #820)	2019-01-19 15:39:46 +00:00
kl	arch/: Clean up some naming and spacing.	2018-06-20 15:38:06 -06:00
lc823450	In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.	2018-12-03 17:41:59 -06:00
lpc17xx_40xx	Merged in jjlange/nuttx/lpc40xx (pull request #946)	2019-07-11 16:50:00 +00:00
lpc31xx
lpc43xx	In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.	2018-12-03 17:41:59 -06:00
lpc54xx	symtab/Makefile: When system wide locale is set (i.e. en_US.UTF-8) then 'read' is ordered after 'readdir' even if separator is set to quotation mark and key set to 2. When C locale is used result is correct.	2019-08-14 11:02:30 -06:00
lpc214x
lpc2378
max326xx	In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.	2018-12-03 17:41:59 -06:00
moxart
nrf52	arch/arm/include/nrf52/ and arch/arm/src/nrf52: 1. Added 52840 family support 2. Use common irq and memory layout header file for 52832 & 52840.	2019-03-12 09:43:49 -06:00
nuc1xx	Cosmetic changes to spacing and comments.	2017-04-20 14:08:08 -06:00
s32k1xx	arch/arm/src/s32k1xx: This commit brings in the LPSPI and LPI2C peripheral drivers from the i.MXRT which used the identical IP.	2019-08-21 11:18:40 -06:00
sam34	In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.	2018-12-03 17:41:59 -06:00
sama5
samd2l2	Rename all usage of samdl/SAMDL to samd2l2/SAMD2L2 to make room in the name space for the forthcoming samd5e5/SAMD5E5	2018-07-22 15:54:12 -06:00
samd5e5	configs/metro-m4: Fix RxD interrupt pin selection. The number SERCOM interrupts do not refer to PAD numbers, but to bit positions in the INFLAG register (very tiny footnote in the data sheet). With with final fix, the basic NSH configuration appears fully functional.	2018-09-01 15:29:22 -06:00
samv7	In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.	2018-12-03 17:41:59 -06:00
stm32	Merged in raiden00/nuttx_pe (pull request #796)	2019-01-02 12:12:28 +00:00
stm32f0l0g0	Add support for STM32G070xx	2019-09-17 11:10:38 -06:00
stm32f7	*Merged in zhoukejun/nuttx_nucleo-f767zi (pull request #838)	2019-03-11 03:44:57 +00:00
stm32h7	Reviewed by David Sidrane.	2019-11-18 14:03:38 -06:00
stm32l4	In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.	2018-12-03 17:41:59 -06:00
str71x
tiva	arch/arm/include/tiva/tm4c_irq.h: Fix wrong IRQ vector number.	2019-11-06 20:43:51 -06:00
tms570	arch/arm/include/tms570, arm/src/armv7-r, and arm/src/tms570: Adds support for the TMS570LS3137ZWT and corrects seversl ARMv7-R and TMS570 issues	2018-04-18 08:58:36 -06:00
xmc4	In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.	2018-12-03 17:41:59 -06:00
.gitignore
arch.h
elf.h	arch/arm/include/syscall.h: Add missing inclusion of arch/armv7-r/syscall.h for CortexR.	2019-01-26 07:43:31 -06:00
inttypes.h
irq.h	arch/arm: Add the initial cortex-a7 archtiecture support	2019-03-19 11:51:29 -06:00
limits.h
setjmp.h	arch/arm/include/setjmp.h: Add prototypes for setjmp/longjmp functions.	2019-11-17 08:48:17 -06:00
spinlock.h	Fix some typos	2019-09-17 10:46:23 -06:00
stdarg.h
syscall.h	arch/arm: Add the initial cortex-a7 archtiecture support	2019-03-19 11:51:29 -06:00
tls.h
types.h