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nuttx/arch/mips/src
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Daniel P. Carvalho ecfe2ed4d3 arch/mips/pic32mz: support GPIO interrupts on the PIC32MZ-W1. 
The change notification code assumed the EC/EF layout: the IRQ of an
I/O port was PIC32MZ_IRQ_PORTA plus the port index, and initialization
reset the change notification registers of every port index.  The
PIC32MZ-W1 only implements PORTA, PORTB, PORTC and PORTK, its change
notification vectors are PIC32MZ_IRQ_CNA/CNB/CNC/CNK, and the addresses
of the missing ports D-J belong to other peripherals (I2C1 is at the
PORTE address).

Map the port index to its IRQ through a table on the W1, skip the
unimplemented ports during initialization, and pass the port index to
the common handler as its argument instead of deriving it from the IRQ
number.  Hide the PORTD-PORTJ interrupt options on the W1.

Assisted-by: Claude Code:claude-opus-5-5
Signed-off-by: Daniel P. Carvalho <danieloak@gmail.com>
2026-10-09 17:55:25 +08:00
..
common arch/mips: Add basic support for MIPS Creator CI20 board 2026-07-15 08:02:55 -03:00
jz4780 arch/mips/jz4780: record the running task on interrupt exit. 2026-10-08 09:28:21 -03:00
mips32 arch/mips/pic32mz: initialize both L1 caches when KSEG0 is cacheable. 2026-10-04 17:16:09 -03:00
pic32mx arch/mips/pic32mx: record the running task on interrupt exit. 2026-10-08 09:28:21 -03:00
pic32mz arch/mips/pic32mz: support GPIO interrupts on the PIC32MZ-W1. 2026-10-09 17:55:25 +08:00
.gitignore
Makefile mips/Makefile: Add nuttx build with CONFIG_ALLSYMS enabled. 2026-08-11 09:53:38 -03:00