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8e6b925200
Implement the MTD write callback when CONFIG_MTD_BYTE_WRITE is enabled, allowing unaligned byte writes without changing existing block operations. Reject ranges outside the physical device and return zero for valid empty writes without SPI traffic. Use the initialized SPI device ID, hold the bus lock across the request, and issue write-enable for each transfer. With CONFIG_RAMTRON_CHUNKING, split writes at the write-buffer boundaries of chunk-limited parts. Document the optional callback and its bounds and chunk behavior. Verified with mocked-SPI host tests, driver compilation with byte writes and chunking enabled/disabled, and a Conductor STM32H743BI hardware test covering single-byte and unaligned writes, surrounding-byte preservation, invalid ranges, and restoration of the original FRAM contents. Hardware coverage is limited to the installed 32 KiB part. Assisted-by: Codex:GPT-6 Signed-off-by: jsanchez-2g <jsanchez@2g-eng.com>
1078 lines
35 KiB
C
1078 lines
35 KiB
C
/****************************************************************************
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* drivers/mtd/ramtron.c
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* OPTIONS:
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* - additional non-jedec standard device: FM25H20
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* must be enabled with the CONFIG_RAMTRON_FRAM_NON_JEDEC=y
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*
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* NOTE:
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* - frequency is fixed to desired max by RAMTRON_INIT_CLK_MAX if new
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* devices with different speed arrive, use the table to handle freq
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* change and to fit all devices. Note that STM32_SPI driver is prone
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* to too high freq. parameters and limit it within physical constraints.
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* The speed may be changed through ioctl MTDIOC_SETSPEED
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*
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* TODO:
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* - add support for sleep
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* - add support for faster read FSTRD command
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*/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <inttypes.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <stdlib.h>
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#include <errno.h>
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#include <nuttx/debug.h>
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#include <assert.h>
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#include <nuttx/kmalloc.h>
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#include <nuttx/fs/ioctl.h>
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#include <nuttx/spi/spi.h>
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#include <nuttx/mtd/mtd.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Used to abort the write wait */
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#ifndef CONFIG_MTD_RAMTRON_WRITEWAIT_COUNT
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# define CONFIG_MTD_RAMTRON_WRITEWAIT_COUNT 100
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#endif
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/* RAMTRON devices are flat!
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* For purpose of the VFAT file system we emulate the following
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* configuration:
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*/
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#define RAMTRON_EMULATE_SECTOR_SHIFT CONFIG_RAMTRON_EMULATE_SECTOR_SHIFT
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#define RAMTRON_EMULATE_PAGE_SHIFT CONFIG_RAMTRON_EMULATE_PAGE_SHIFT
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#define RAMTRON_EMULATE_PAGE_SIZE (1 << RAMTRON_EMULATE_PAGE_SHIFT)
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/* RAMTRON Identification register values */
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#define RAMTRON_MANUFACTURER 0x7f
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#define RAMTRON_MEMORY_TYPE 0xc2
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/* Instructions:
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* Command Value N Description Addr Dummy Data
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*/
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#define RAMTRON_WREN 0x06 /* 1 Write Enable 0 0 0 */
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#define RAMTRON_WRDI 0x04 /* 1 Write Disable 0 0 0 */
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#define RAMTRON_RDSR 0x05 /* 1 Read Status Register 0 0 >=1 */
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#define RAMTRON_WRSR 0x01 /* 1 Write Status Register 0 0 1 */
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#define RAMTRON_READ 0x03 /* 1 Read Data Bytes A 0 >=1 */
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#define RAMTRON_FSTRD 0x0b /* 1 Higher speed read A 1 >=1 */
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#define RAMTRON_WRITE 0x02 /* 1 Write A 0 1-256 */
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#define RAMTRON_SLEEP 0xb9 /* TODO: */
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#define RAMTRON_RDID 0x9f /* 1 Read Identification 0 0 1-3 */
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#define RAMTRON_SN 0xc3 /* TODO: */
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/* Status register bit definitions */
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/* Bit 0: Res 0 */
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#define RAMTRON_SR_WEL (1 << 1) /* Bit 1: Write enable latch bit */
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#define RAMTRON_SR_BP_SHIFT (2) /* Bits 2-4: Block protect bits */
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#define RAMTRON_SR_BP_MASK (3 << RAMTRON_SR_BP_SHIFT)
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#define RAMTRON_SR_BP_NONE (0 << RAMTRON_SR_BP_SHIFT) /* Unprotected */
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#define RAMTRON_SR_BP_UPPERQTR (1 << RAMTRON_SR_BP_SHIFT) /* Upper quarter */
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#define RAMTRON_SR_BP_UPPERHALF (2 << RAMTRON_SR_BP_SHIFT) /* Upper half */
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#define RAMTRON_SR_BP_ALL (3 << RAMTRON_SR_BP_SHIFT) /* All sectors */
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#define RAMTRON_SR_BP_SHIFT (2) /* Bits 4-6: Reserved Always 0 */
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#define RAMTRON_SR_WPEN (1 << 7) /* Bit 7: Status register write protect */
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#define RAMTRON_DUMMY 0xa5
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/* Defines the initial speed compatible with all devices. In case of RAMTRON
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* the defined devices within the part list have all the same speed.
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*/
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#define RAMTRON_INIT_CLK_MAX 40000000UL
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/****************************************************************************
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* Private Types
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****************************************************************************/
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struct ramtron_parts_s
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{
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FAR const char *name;
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uint8_t id1;
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uint8_t id2;
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uint32_t size;
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uint8_t addr_len;
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uint32_t speed;
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#ifdef CONFIG_RAMTRON_CHUNKING
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bool chunked; /* True: write buffer size limitations */
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uint16_t chunksize; /* Write chunk Size */
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#endif
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};
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/* This type represents the state of the MTD device. The struct mtd_dev_s
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* must appear at the beginning of the definition so that you can freely
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* cast between pointers to struct mtd_dev_s and struct ramtron_dev_s.
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*/
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struct ramtron_dev_s
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{
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struct mtd_dev_s mtd; /* MTD interface */
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FAR struct spi_dev_s *dev; /* Saved SPI interface instance */
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uint8_t sectorshift;
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uint8_t pageshift;
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uint16_t devid; /* SPI device ID to manage CS lines in board */
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uint32_t nsectors;
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uint32_t npages;
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uint32_t speed; /* Overridable via ioctl */
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FAR const struct ramtron_parts_s *part; /* Part instance */
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};
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/****************************************************************************
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* Supported Part Lists
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****************************************************************************/
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static const struct ramtron_parts_s g_ramtron_parts[] =
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{
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{
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"FM25V01", /* name */
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0x21, /* id1 */
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0x00, /* id2 */
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16L * 1024L, /* size */
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2, /* addr_len */
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RAMTRON_INIT_CLK_MAX /* speed */
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#ifdef CONFIG_RAMTRON_CHUNKING
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, false, /* chunked */
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RAMTRON_EMULATE_PAGE_SIZE /* chunksize */
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#endif
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},
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{
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"FM25V01A", /* name */
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0x21, /* id1 */
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0x08, /* id2 */
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16L * 1024L, /* size */
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2, /* addr_len */
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RAMTRON_INIT_CLK_MAX /* speed */
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#ifdef CONFIG_RAMTRON_CHUNKING
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, false, /* chunked */
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RAMTRON_EMULATE_PAGE_SIZE /* chunksize */
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#endif
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},
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{
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"FM25V02", /* name */
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0x22, /* id1 */
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0x00, /* id2 */
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32L * 1024L, /* size */
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2, /* addr_len */
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RAMTRON_INIT_CLK_MAX /* speed */
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#ifdef CONFIG_RAMTRON_CHUNKING
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, false, /* chunked */
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RAMTRON_EMULATE_PAGE_SIZE /* chunksize */
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#endif
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},
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{
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"FM25V02A", /* name */
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0x22, /* id1 */
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0x08, /* id2 */
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32L * 1024L, /* size */
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2, /* addr_len */
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RAMTRON_INIT_CLK_MAX /* speed */
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#ifdef CONFIG_RAMTRON_CHUNKING
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, false, /* chunked */
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RAMTRON_EMULATE_PAGE_SIZE /* chunksize */
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#endif
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},
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{
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"FM25V02A-DGQ", /* name */
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0x22, /* id1 */
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0x48, /* id2 */
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32L * 1024L, /* size */
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2, /* addr_len */
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RAMTRON_INIT_CLK_MAX /* speed */
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#ifdef CONFIG_RAMTRON_CHUNKING
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, false, /* chunked */
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RAMTRON_EMULATE_PAGE_SIZE /* chunksize */
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#endif
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},
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{
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"FM25VN02", /* name */
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0x22, /* id1 */
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0x01, /* id2 */
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32L * 1024L, /* size */
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2, /* addr_len */
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RAMTRON_INIT_CLK_MAX /* speed */
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#ifdef CONFIG_RAMTRON_CHUNKING
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, false, /* chunked */
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RAMTRON_EMULATE_PAGE_SIZE /* chunksize */
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#endif
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},
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{
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"FM25V05", /* name */
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0x23, /* id1 */
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0x00, /* id2 */
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64L * 1024L, /* size */
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2, /* addr_len */
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RAMTRON_INIT_CLK_MAX /* speed */
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#ifdef CONFIG_RAMTRON_CHUNKING
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, false, /* chunked */
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RAMTRON_EMULATE_PAGE_SIZE /* chunksize */
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#endif
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},
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{
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"FM25VN05", /* name */
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0x23, /* id1 */
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0x01, /* id2 */
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64L * 1024L, /* size */
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2, /* addr_len */
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RAMTRON_INIT_CLK_MAX /* speed */
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#ifdef CONFIG_RAMTRON_CHUNKING
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, false, /* chunked */
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RAMTRON_EMULATE_PAGE_SIZE /* chunksize */
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#endif
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},
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{
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"FM25V10", /* name */
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0x24, /* id1 */
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0x00, /* id2 */
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128L * 1024L, /* size */
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3, /* addr_len */
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RAMTRON_INIT_CLK_MAX /* speed */
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#ifdef CONFIG_RAMTRON_CHUNKING
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, false, /* chunked */
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RAMTRON_EMULATE_PAGE_SIZE /* chunksize */
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#endif
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},
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{
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"FM25VN10", /* name */
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0x24, /* id1 */
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0x01, /* id2 */
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128L * 1024L, /* size */
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3, /* addr_len */
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RAMTRON_INIT_CLK_MAX /* speed */
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#ifdef CONFIG_RAMTRON_CHUNKING
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, false, /* chunked */
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RAMTRON_EMULATE_PAGE_SIZE /* chunksize */
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#endif
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},
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{
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"FM25V20A", /* name */
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0x25, /* id1 */
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0x08, /* id2 */
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256L * 1024L, /* size */
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3, /* addr_len */
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RAMTRON_INIT_CLK_MAX /* speed */
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#ifdef CONFIG_RAMTRON_CHUNKING
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, false, /* chunked */
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RAMTRON_EMULATE_PAGE_SIZE /* chunksize */
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#endif
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},
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{
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"CY15B104Q", /* name */
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0x26, /* id1 */
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0x08, /* id2 */
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512L * 1024L, /* size */
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3, /* addr_len */
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RAMTRON_INIT_CLK_MAX /* speed */
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#ifdef CONFIG_RAMTRON_CHUNKING
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, false, /* chunked */
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RAMTRON_EMULATE_PAGE_SIZE /* chunksize */
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#endif
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},
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{
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"MB85RS1MT", /* name */
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0x27, /* id1 */
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0x03, /* id2 */
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128L * 1024L, /* size */
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3, /* addr_len */
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25000000 /* speed */
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#ifdef CONFIG_RAMTRON_CHUNKING
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, false, /* chunked */
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RAMTRON_EMULATE_PAGE_SIZE /* chunksize */
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#endif
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},
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{
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"MB85RS2MT", /* name */
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0x48, /* id1 */
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0x03, /* id2 */
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256L * 1024L, /* size */
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3, /* addr_len */
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25000000 /* speed */
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#ifdef CONFIG_RAMTRON_CHUNKING
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, false, /* chunked */
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RAMTRON_EMULATE_PAGE_SIZE /* chunksize */
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#endif
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},
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{
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"MB85RS64V", /* name */
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0x03, /* id1 */
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0x02, /* id2 */
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8L * 1024L, /* size */
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2, /* addr_len */
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20000000 /* speed */
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#ifdef CONFIG_RAMTRON_CHUNKING
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, false, /* chunked */
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RAMTRON_EMULATE_PAGE_SIZE /* chunksize */
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#endif
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},
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{
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"MB85RS256B", /* name */
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0x05, /* id1 */
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0x09, /* id2 */
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32L * 1024L, /* size */
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2, /* addr_len */
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25000000 /* speed */
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#ifdef CONFIG_RAMTRON_CHUNKING
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, false, /* chunked */
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RAMTRON_EMULATE_PAGE_SIZE /* chunksize */
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#endif
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},
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#ifdef CONFIG_RAMTRON_CHUNKING
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{
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"MB85AS4MT", /* name */
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0xc9, /* id1 */
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0x03, /* id2 */
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512L * 1024L, /* size */
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3, /* addr_len */
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RAMTRON_INIT_CLK_MAX, /* speed */
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true, /* chunked */
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256 /* chunksize */
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},
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#endif
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#ifdef CONFIG_RAMTRON_FRAM_NON_JEDEC
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{
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"FM25H20", /* name */
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0xff, /* id1 */
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0xff, /* id2 */
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256L * 1024L, /* size */
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3, /* addr_len */
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RAMTRON_INIT_CLK_MAX /* speed */
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#ifdef CONFIG_RAMTRON_CHUNKING
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, false, /* chunked */
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RAMTRON_EMULATE_PAGE_SIZE /* chunksize */
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#endif
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},
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#endif
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{
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NULL, /* name */
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0, /* id1 */
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0, /* id2 */
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0, /* size */
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0, /* addr_len */
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0 /* speed */
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#ifdef CONFIG_RAMTRON_CHUNKING
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, false, /* chunked */
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0, /* chunksize */
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#endif
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}
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};
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/****************************************************************************
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* Private Function Prototypes
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****************************************************************************/
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/* Helpers */
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static void ramtron_lock(FAR struct ramtron_dev_s *priv);
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static inline void ramtron_unlock(FAR struct spi_dev_s *dev);
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static inline int ramtron_readid(struct ramtron_dev_s *priv);
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static void ramtron_writeenable(struct ramtron_dev_s *priv);
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static inline int ramtron_pagewrite(struct ramtron_dev_s *priv,
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FAR const uint8_t *buffer,
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off_t offset,
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size_t pagesize);
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/* MTD driver methods */
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static int ramtron_erase(FAR struct mtd_dev_s *dev,
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off_t startblock,
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size_t nblocks);
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static ssize_t ramtron_bread(FAR struct mtd_dev_s *dev,
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off_t startblock,
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size_t nblocks, FAR uint8_t *buf);
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#ifdef CONFIG_RAMTRON_CHUNKING
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static ssize_t ramtron_bwrite_nonchunked(FAR struct mtd_dev_s *dev,
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off_t startblock,
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size_t nblocks,
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FAR const uint8_t *buffer);
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static ssize_t ramtron_bwrite_chunked(FAR struct mtd_dev_s *dev,
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off_t startblock,
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size_t nblocks,
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FAR const uint8_t *buf);
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#endif
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static ssize_t ramtron_bwrite(FAR struct mtd_dev_s *dev,
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off_t startblock,
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size_t nblocks,
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FAR const uint8_t *buf);
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static ssize_t ramtron_read(FAR struct mtd_dev_s *dev,
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off_t offset,
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size_t nbytes,
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FAR uint8_t *buffer);
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#ifdef CONFIG_MTD_BYTE_WRITE
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static ssize_t ramtron_write(FAR struct mtd_dev_s *dev, off_t offset,
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size_t nbytes, FAR const uint8_t *buffer);
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#endif
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static int ramtron_ioctl(FAR struct mtd_dev_s *dev,
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int cmd,
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unsigned long arg);
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: ramtron_lock
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****************************************************************************/
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static void ramtron_lock(FAR struct ramtron_dev_s *priv)
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{
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FAR struct spi_dev_s *dev = priv->dev;
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/* On SPI buses where there are multiple devices, it will be necessary to
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* lock SPI to have exclusive access to the buses for a sequence of
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* transfers. The bus should be locked before the chip is selected.
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*
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* This is a blocking call and will not return until we have exclusive
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* access to the SPI bus.
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* We will retain that exclusive access until the bus is unlocked.
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*/
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SPI_LOCK(dev, true);
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/* After locking the SPI bus, the we also need call the setfrequency,
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* setbits, and setmode methods to make sure that the SPI is properly
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* configured for the device.
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* If the SPI bus is being shared, then it may have been left in an
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* incompatible state.
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*/
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SPI_SETMODE(dev, SPIDEV_MODE3);
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SPI_SETBITS(dev, 8);
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SPI_HWFEATURES(dev, 0);
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SPI_SETFREQUENCY(dev, priv->speed);
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}
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/****************************************************************************
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* Name: ramtron_unlock
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****************************************************************************/
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static inline void ramtron_unlock(FAR struct spi_dev_s *dev)
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{
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SPI_LOCK(dev, false);
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}
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|
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/****************************************************************************
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* Name: ramtron_readid
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****************************************************************************/
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static inline int ramtron_readid(struct ramtron_dev_s *priv)
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{
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uint16_t manufacturer;
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uint16_t memory;
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uint16_t capacity;
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uint16_t part;
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|
int i;
|
|
|
|
finfo("priv: %p\n", priv);
|
|
|
|
/* Lock the SPI bus, configure the bus, and select this FLASH part. */
|
|
|
|
ramtron_lock(priv);
|
|
SPI_SELECT(priv->dev, SPIDEV_FLASH(priv->devid), true);
|
|
|
|
/* Send the "Read ID (RDID)" command */
|
|
|
|
SPI_SEND(priv->dev, RAMTRON_RDID);
|
|
|
|
/* Read the first six manufacturer ID bytes. */
|
|
|
|
for (i = 0; i < 6; i++)
|
|
{
|
|
/* Read the next manufacturer byte */
|
|
|
|
manufacturer = SPI_SEND(priv->dev, RAMTRON_DUMMY);
|
|
|
|
/* Fujitsu parts such as MB85RS1MT only have 1-byte for the
|
|
* manufacturer ID. The manufacturer code is "0x4".
|
|
*/
|
|
|
|
if (i == 0 && manufacturer == 0x04)
|
|
{
|
|
break;
|
|
}
|
|
}
|
|
|
|
memory = SPI_SEND(priv->dev, RAMTRON_DUMMY);
|
|
capacity = SPI_SEND(priv->dev, RAMTRON_DUMMY); /* FRAM ID1 */
|
|
part = SPI_SEND(priv->dev, RAMTRON_DUMMY); /* FRAM ID2 */
|
|
|
|
/* Deselect the FLASH and unlock the bus */
|
|
|
|
SPI_SELECT(priv->dev, SPIDEV_FLASH(priv->devid), false);
|
|
ramtron_unlock(priv->dev);
|
|
|
|
/* Select part from the part list */
|
|
|
|
for (priv->part = g_ramtron_parts;
|
|
priv->part->name != NULL &&
|
|
!(priv->part->id1 == capacity && priv->part->id2 == part);
|
|
priv->part++);
|
|
|
|
if (priv->part->name != NULL)
|
|
{
|
|
UNUSED(manufacturer); /* Eliminate warnings when debug is off */
|
|
UNUSED(memory); /* Eliminate warnings when debug is off */
|
|
|
|
finfo("RAMTRON %s of size %" PRIu32 " bytes (mf:%02" PRIx16 " mem:%02"
|
|
PRIx16 " cap:%02" PRIx16 " part:%02" PRIx16 ")\n",
|
|
priv->part->name, priv->part->size, manufacturer, memory,
|
|
capacity, part);
|
|
|
|
priv->sectorshift = RAMTRON_EMULATE_SECTOR_SHIFT;
|
|
priv->nsectors = priv->part->size /
|
|
(1 << RAMTRON_EMULATE_SECTOR_SHIFT);
|
|
priv->pageshift = RAMTRON_EMULATE_PAGE_SHIFT;
|
|
priv->npages = priv->part->size /
|
|
(1 << RAMTRON_EMULATE_PAGE_SHIFT);
|
|
priv->speed = priv->part->speed;
|
|
return OK;
|
|
}
|
|
|
|
finfo("RAMTRON device not found\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: ramtron_writeenable
|
|
****************************************************************************/
|
|
|
|
static void ramtron_writeenable(struct ramtron_dev_s *priv)
|
|
{
|
|
/* Select this FLASH part */
|
|
|
|
SPI_SELECT(priv->dev, SPIDEV_FLASH(priv->devid), true);
|
|
|
|
/* Send "Write Enable (WREN)" command */
|
|
|
|
SPI_SEND(priv->dev, RAMTRON_WREN);
|
|
|
|
/* Deselect the FLASH */
|
|
|
|
SPI_SELECT(priv->dev, SPIDEV_FLASH(priv->devid), false);
|
|
finfo("Enabled\n");
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: ramtron_sendaddr
|
|
****************************************************************************/
|
|
|
|
static inline void ramtron_sendaddr(const struct ramtron_dev_s *priv,
|
|
uint32_t addr)
|
|
{
|
|
DEBUGASSERT(priv->part->addr_len == 3 || priv->part->addr_len == 2);
|
|
|
|
if (priv->part->addr_len == 3)
|
|
{
|
|
SPI_SEND(priv->dev, (addr >> 16) & 0xff);
|
|
}
|
|
|
|
SPI_SEND(priv->dev, (addr >> 8) & 0xff);
|
|
SPI_SEND(priv->dev, addr & 0xff);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: ramtron_pagewrite
|
|
****************************************************************************/
|
|
|
|
static inline int ramtron_pagewrite(struct ramtron_dev_s *priv,
|
|
FAR const uint8_t *buffer, off_t page,
|
|
size_t pagesize)
|
|
{
|
|
off_t offset = page * pagesize;
|
|
|
|
finfo("page: %08lx offset: %08lx\n", (long)page, (long)offset);
|
|
|
|
/* Enable the write access to the FLASH */
|
|
|
|
ramtron_writeenable(priv);
|
|
|
|
/* Select this FLASH part */
|
|
|
|
SPI_SELECT(priv->dev, SPIDEV_FLASH(priv->devid), true);
|
|
|
|
/* Send "Page Program (PP)" command */
|
|
|
|
SPI_SEND(priv->dev, RAMTRON_WRITE);
|
|
|
|
/* Send the page offset high byte first. */
|
|
|
|
ramtron_sendaddr(priv, offset);
|
|
|
|
/* Then write the specified number of bytes */
|
|
|
|
SPI_SNDBLOCK(priv->dev, buffer, pagesize);
|
|
|
|
/* Deselect the FLASH: Chip Select high */
|
|
|
|
SPI_SELECT(priv->dev, SPIDEV_FLASH(priv->devid), false);
|
|
finfo("Written\n");
|
|
|
|
return OK;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: ramtron_erase
|
|
****************************************************************************/
|
|
|
|
static int ramtron_erase(FAR struct mtd_dev_s *dev,
|
|
off_t startblock,
|
|
size_t nblocks)
|
|
{
|
|
finfo("startblock: %08lx nblocks: %d\n",
|
|
(unsigned long)startblock,
|
|
(int)nblocks);
|
|
finfo("On RAMTRON devices erasing makes no sense, returning as OK\n");
|
|
return (int)nblocks;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: ramtron_bread
|
|
****************************************************************************/
|
|
|
|
static ssize_t ramtron_bread(FAR struct mtd_dev_s *dev, off_t startblock,
|
|
size_t nblocks, FAR uint8_t *buffer)
|
|
{
|
|
FAR struct ramtron_dev_s *priv = (FAR struct ramtron_dev_s *)dev;
|
|
ssize_t nbytes;
|
|
|
|
finfo("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
|
|
|
|
/* On this device, we can handle the block read just like the byte-oriented
|
|
* read
|
|
*/
|
|
|
|
nbytes = ramtron_read(dev, startblock << priv->pageshift,
|
|
nblocks << priv->pageshift, buffer);
|
|
if (nbytes > 0)
|
|
{
|
|
return nbytes >> priv->pageshift;
|
|
}
|
|
|
|
return (int)nbytes;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: ramtron_bwrite/ramtron_bwrite_nonchunked
|
|
****************************************************************************/
|
|
|
|
#ifdef CONFIG_RAMTRON_CHUNKING
|
|
static ssize_t ramtron_bwrite_nonchunked(FAR struct mtd_dev_s *dev,
|
|
off_t startblock,
|
|
size_t nblocks,
|
|
FAR const uint8_t *buffer)
|
|
#else
|
|
static ssize_t ramtron_bwrite(FAR struct mtd_dev_s *dev,
|
|
off_t startblock,
|
|
size_t nblocks,
|
|
FAR const uint8_t *buffer)
|
|
#endif
|
|
{
|
|
FAR struct ramtron_dev_s *priv = (FAR struct ramtron_dev_s *)dev;
|
|
size_t blocksleft = nblocks;
|
|
|
|
finfo("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
|
|
DEBUGASSERT(priv != NULL && buffer != NULL);
|
|
|
|
/* Lock the SPI bus and write each page to FLASH */
|
|
|
|
ramtron_lock(priv);
|
|
while (blocksleft-- > 0)
|
|
{
|
|
if (ramtron_pagewrite(priv, buffer, startblock, 1 << priv->pageshift))
|
|
{
|
|
nblocks = 0;
|
|
break;
|
|
}
|
|
|
|
startblock++;
|
|
}
|
|
|
|
ramtron_unlock(priv->dev);
|
|
return nblocks;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: ramtron_bwrite_chunked
|
|
****************************************************************************/
|
|
|
|
#ifdef CONFIG_RAMTRON_CHUNKING
|
|
static ssize_t ramtron_bwrite_chunked(FAR struct mtd_dev_s *dev,
|
|
off_t startblock,
|
|
size_t nblocks,
|
|
FAR const uint8_t *buffer)
|
|
{
|
|
FAR struct ramtron_dev_s *priv = (FAR struct ramtron_dev_s *)dev;
|
|
FAR const struct ramtron_parts_s *part;
|
|
size_t blocksleft = nblocks;
|
|
uint32_t p;
|
|
uint32_t writesplits;
|
|
off_t newstartblock;
|
|
|
|
finfo("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
|
|
|
|
DEBUGASSERT(priv != NULL && priv->part != NULL && buffer != NULL);
|
|
part = priv->part;
|
|
|
|
writesplits = (1 << priv->pageshift) / part->chunksize;
|
|
newstartblock = startblock * writesplits;
|
|
|
|
/* Lock the SPI bus and write each page to FLASH */
|
|
|
|
ramtron_lock(priv);
|
|
while (blocksleft-- > 0)
|
|
{
|
|
/* Split writes in chunksize chunks */
|
|
|
|
for (p = 0; p < writesplits; p++)
|
|
{
|
|
if (ramtron_pagewrite(priv,
|
|
buffer + p * part->chunksize,
|
|
newstartblock,
|
|
part->chunksize))
|
|
{
|
|
nblocks = 0;
|
|
goto out;
|
|
}
|
|
|
|
newstartblock++;
|
|
}
|
|
}
|
|
|
|
out:
|
|
ramtron_unlock(priv->dev);
|
|
return nblocks;
|
|
}
|
|
#endif
|
|
|
|
/****************************************************************************
|
|
* Name: ramtron_bwrite
|
|
****************************************************************************/
|
|
|
|
#ifdef CONFIG_RAMTRON_CHUNKING
|
|
static ssize_t ramtron_bwrite(FAR struct mtd_dev_s *dev, off_t startblock,
|
|
size_t nblocks, FAR const uint8_t *buffer)
|
|
{
|
|
FAR struct ramtron_dev_s *priv = (FAR struct ramtron_dev_s *)dev;
|
|
FAR const struct ramtron_parts_s *part;
|
|
|
|
DEBUGASSERT(priv != NULL && priv->part != NULL && buffer != NULL);
|
|
part = priv->part;
|
|
|
|
/* Handle parts that require chunked output differently */
|
|
|
|
if (part->chunked)
|
|
{
|
|
return ramtron_bwrite_chunked(dev, startblock, nblocks, buffer);
|
|
}
|
|
else
|
|
{
|
|
return ramtron_bwrite_nonchunked(dev, startblock, nblocks, buffer);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
/****************************************************************************
|
|
* Name: ramtron_read
|
|
****************************************************************************/
|
|
|
|
static ssize_t ramtron_read(FAR struct mtd_dev_s *dev,
|
|
off_t offset,
|
|
size_t nbytes,
|
|
FAR uint8_t *buffer)
|
|
{
|
|
FAR struct ramtron_dev_s *priv = (FAR struct ramtron_dev_s *)dev;
|
|
|
|
finfo("offset: %08lx nbytes: %d\n", (long)offset, (int)nbytes);
|
|
|
|
/* Lock the SPI bus NOW because the ramtron_waitwritecomplete call must be
|
|
* executed with the bus locked.
|
|
*/
|
|
|
|
ramtron_lock(priv);
|
|
|
|
/* Select this FLASH part */
|
|
|
|
SPI_SELECT(priv->dev, SPIDEV_FLASH(priv->devid), true);
|
|
|
|
/* Send "Read from Memory " instruction */
|
|
|
|
SPI_SEND(priv->dev, RAMTRON_READ);
|
|
|
|
/* Send the page offset high byte first. */
|
|
|
|
ramtron_sendaddr(priv, offset);
|
|
|
|
/* Then read all of the requested bytes */
|
|
|
|
SPI_RECVBLOCK(priv->dev, buffer, nbytes);
|
|
|
|
/* Deselect the FLASH and unlock the SPI bus */
|
|
|
|
SPI_SELECT(priv->dev, SPIDEV_FLASH(priv->devid), false);
|
|
ramtron_unlock(priv->dev);
|
|
|
|
finfo("return nbytes: %d\n", (int)nbytes);
|
|
return nbytes;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: ramtron_write
|
|
****************************************************************************/
|
|
|
|
#ifdef CONFIG_MTD_BYTE_WRITE
|
|
static ssize_t ramtron_write(FAR struct mtd_dev_s *dev, off_t offset,
|
|
size_t nbytes, FAR const uint8_t *buffer)
|
|
{
|
|
FAR struct ramtron_dev_s *priv = (FAR struct ramtron_dev_s *)dev;
|
|
size_t remaining = nbytes;
|
|
size_t count;
|
|
#ifdef CONFIG_RAMTRON_CHUNKING
|
|
size_t available;
|
|
#endif
|
|
|
|
/* Reject requests that could wrap around the physical device. */
|
|
|
|
if (offset < 0 || offset > priv->part->size ||
|
|
nbytes > priv->part->size - (uint32_t)offset)
|
|
{
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (nbytes == 0)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
DEBUGASSERT(buffer != NULL);
|
|
ramtron_lock(priv);
|
|
|
|
while (remaining > 0)
|
|
{
|
|
count = remaining;
|
|
#ifdef CONFIG_RAMTRON_CHUNKING
|
|
if (priv->part->chunked)
|
|
{
|
|
/* Do not cross a write-buffer boundary on chunk-limited parts. */
|
|
|
|
available = priv->part->chunksize -
|
|
offset % priv->part->chunksize;
|
|
if (count > available)
|
|
{
|
|
count = available;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
ramtron_writeenable(priv);
|
|
SPI_SELECT(priv->dev, SPIDEV_FLASH(priv->devid), true);
|
|
SPI_SEND(priv->dev, RAMTRON_WRITE);
|
|
ramtron_sendaddr(priv, offset);
|
|
SPI_SNDBLOCK(priv->dev, buffer, count);
|
|
SPI_SELECT(priv->dev, SPIDEV_FLASH(priv->devid), false);
|
|
|
|
offset += count;
|
|
buffer += count;
|
|
remaining -= count;
|
|
}
|
|
|
|
ramtron_unlock(priv->dev);
|
|
return nbytes;
|
|
}
|
|
#endif
|
|
|
|
/****************************************************************************
|
|
* Name: ramtron_ioctl
|
|
****************************************************************************/
|
|
|
|
static int ramtron_ioctl(FAR struct mtd_dev_s *dev,
|
|
int cmd,
|
|
unsigned long arg)
|
|
{
|
|
FAR struct ramtron_dev_s *priv = (FAR struct ramtron_dev_s *)dev;
|
|
int ret = -EINVAL; /* Assume good command with bad parameters */
|
|
|
|
finfo("cmd: %d\n", cmd);
|
|
|
|
switch (cmd)
|
|
{
|
|
case MTDIOC_GEOMETRY:
|
|
{
|
|
FAR struct mtd_geometry_s *geo =
|
|
(FAR struct mtd_geometry_s *)((uintptr_t)arg);
|
|
|
|
if (geo)
|
|
{
|
|
memset(geo, 0, sizeof(*geo));
|
|
|
|
/* Populate the geometry structure with information need to
|
|
* know the capacity and how to access the device.
|
|
*
|
|
* NOTE:
|
|
* that the device is treated as though it where just an array
|
|
* of fixed size blocks. That is most likely not true, but the
|
|
* client will expect the device logic to do whatever is
|
|
* necessary to make it appear so.
|
|
*/
|
|
|
|
geo->blocksize = (1 << priv->pageshift);
|
|
geo->erasesize = (1 << priv->sectorshift);
|
|
geo->neraseblocks = priv->nsectors;
|
|
ret = OK;
|
|
|
|
finfo("blocksize: %ld erasesize: %ld neraseblocks: %ld\n",
|
|
geo->blocksize, geo->erasesize, geo->neraseblocks);
|
|
}
|
|
}
|
|
break;
|
|
|
|
case BIOC_PARTINFO:
|
|
{
|
|
FAR struct partition_info_s *info =
|
|
(FAR struct partition_info_s *)arg;
|
|
|
|
if (info != NULL)
|
|
{
|
|
info->numsectors = priv->nsectors *
|
|
(priv->sectorshift - priv->pageshift);
|
|
info->sectorsize = 1 << priv->pageshift;
|
|
info->startsector = 0;
|
|
info->parent[0] = '\0';
|
|
ret = OK;
|
|
}
|
|
}
|
|
break;
|
|
|
|
case MTDIOC_BULKERASE:
|
|
finfo("BULDERASE: Makes no sense in ramtron.\n");
|
|
finfo("BULDERASE: Let's confirm operation as OK\n");
|
|
ret = OK;
|
|
break;
|
|
|
|
#ifdef CONFIG_RAMTRON_SETSPEED
|
|
case MTDIOC_SETSPEED:
|
|
{
|
|
if (arg > 0 && arg <= RAMTRON_INIT_CLK_MAX)
|
|
{
|
|
priv->speed = arg;
|
|
finfo("set bus speed to %lu\n", priv->speed);
|
|
ret = OK;
|
|
}
|
|
}
|
|
break;
|
|
#endif
|
|
|
|
default:
|
|
ret = -ENOTTY; /* Bad command */
|
|
break;
|
|
}
|
|
|
|
finfo("return %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Public Functions
|
|
****************************************************************************/
|
|
|
|
/****************************************************************************
|
|
* Name: ramtron_initialize
|
|
*
|
|
* Description:
|
|
* Create an initialize MTD device instance.
|
|
* MTD devices are not registered in the file system, but are created
|
|
* as instances that can be bound to other functions
|
|
* (such as a block or character driver front end).
|
|
*
|
|
* Note:
|
|
* This implementation can handle multiple FLASH parts per SPI device by
|
|
* using the spi_devid to handle chip select between devices. The spi_devid
|
|
* passed to this function must be handled by the corresponding spi select
|
|
* function in board files.
|
|
****************************************************************************/
|
|
|
|
FAR struct mtd_dev_s *ramtron_initialize(FAR struct spi_dev_s *dev,
|
|
uint16_t spi_devid)
|
|
{
|
|
FAR struct ramtron_dev_s *priv;
|
|
|
|
finfo("dev: %p\n", dev);
|
|
|
|
/* Allocate a state structure (we allocate the structure instead of using
|
|
* a fixed, static allocation so that we can handle multiple FLASH devices.
|
|
*/
|
|
|
|
priv = (FAR struct ramtron_dev_s *)
|
|
kmm_zalloc(sizeof(struct ramtron_dev_s));
|
|
if (priv)
|
|
{
|
|
/* Initialize the allocated structure. (unsupported methods were
|
|
* nullified by kmm_zalloc).
|
|
*/
|
|
|
|
priv->mtd.erase = ramtron_erase;
|
|
priv->mtd.bread = ramtron_bread;
|
|
priv->mtd.bwrite = ramtron_bwrite;
|
|
priv->mtd.read = ramtron_read;
|
|
#ifdef CONFIG_MTD_BYTE_WRITE
|
|
priv->mtd.write = ramtron_write;
|
|
#endif
|
|
priv->mtd.ioctl = ramtron_ioctl;
|
|
priv->mtd.name = "ramtron";
|
|
priv->dev = dev;
|
|
priv->devid = spi_devid;
|
|
|
|
/* Deselect the FLASH */
|
|
|
|
SPI_SELECT(dev, SPIDEV_FLASH(priv->devid), false);
|
|
|
|
/* Identify the FLASH chip and get its capacity */
|
|
|
|
if (ramtron_readid(priv) != OK)
|
|
{
|
|
/* Unrecognized! Discard all of that work we just did and
|
|
* return NULL
|
|
*/
|
|
|
|
kmm_free(priv);
|
|
return NULL;
|
|
}
|
|
}
|
|
|
|
/* Return the implementation-specific state structure as the MTD device */
|
|
|
|
finfo("Return %p\n", priv);
|
|
return (FAR struct mtd_dev_s *)priv;
|
|
}
|