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54040c6888
Add support for ARMv6-M and ARMv8-M Baseline architectures (Cortex-M0/M0+/M23) in the mcount profiling function. These cores only support limited Thumb-1 instruction set and require different assembly instructions compared to ARMv7-M and higher. Changes: - Use MOVS+BICS instead of BIC for bit clearing on M0/M23 - Separate register restore for limited push/pop instructions - Use BX instead of direct POP to PC on M0/M23 Signed-off-by: yinshengkai <yinshengkai@bytedance.com>
57 lines
2.3 KiB
ArmAsm
57 lines
2.3 KiB
ArmAsm
/****************************************************************************
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* libs/libc/machine/arm/arch_mcount.S
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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.globl __gnu_mcount_nc
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.syntax unified
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.file "mcount.S"
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.type __gnu_mcount_nc, %function
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__gnu_mcount_nc:
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#if defined(CONFIG_ARCH_CORTEXM0) || defined(CONFIG_ARCH_CORTEXM23)
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/* Cortex-M0/M0+/M23 - ARMv6-M and ARMv8-M Baseline */
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/* These cores only support limited Thumb-1 instruction set */
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push {r0, r1, r2, r3, lr} /* Save registers */
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mov r1, lr
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movs r2, #1
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bics r1, r2 /* R1 contains callee address, with thumb bit cleared */
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ldr r0, [sp, #20] /* R0 contains caller address */
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movs r2, #1
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bics r0, r2 /* Clear thumb bit */
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bl mcount_internal /* Jump to internal _mcount() implementation */
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pop {r0, r1, r2, r3, pc} /* Restore r0-r3 and return to caller */
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#else
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/* ARMv7-M/A/R and higher - Full Thumb-2 support */
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push {r0, r1, r2, r3, lr} /* Save registers */
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mov r1, lr
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bic r1, r1, #1 /* R1 contains callee address, with thumb bit cleared */
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ldr r0, [sp, #20] /* R0 contains caller address */
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bic r0, r0, #1 /* Clear thumb bit */
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bl mcount_internal /* Jump to internal _mcount() implementation */
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pop {r0, r1, r2, r3, ip, lr} /* Restore saved registers */
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bx ip /* Return to callee */
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#endif
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.size __gnu_mcount_nc, .-__gnu_mcount_nc
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.end
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