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4dadf28cfb
BREAKING CHANGE: STM32WB Kconfig symbols were renamed from CONFIG_STM32WB_* to CONFIG_STM32_*. Out-of-tree code must update defconfigs and Kconfig references to the new CONFIG_STM32_* names. The custom clock option is a special breaking case that does not follow the family-to-common pattern: CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG was renamed to CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG. Signed-off-by: raiden00pl <raiden00@railab.me>
172 lines
7.5 KiB
C
172 lines
7.5 KiB
C
/****************************************************************************
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* arch/arm/include/stm32wb/chip.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_STM32WB_CHIP_H
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#define __ARCH_ARM_INCLUDE_STM32WB_CHIP_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Prototypes
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****************************************************************************/
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#define STM32_NFSMC 0 /* No FSMC */
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#define STM32_NBTIM 0 /* No basic timers */
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#define STM32_NATIM 1 /* One advanced timers TIM1 */
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#define STM32_NGTIM32 1 /* 32-bit general timers TIM2 with DMA */
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#define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
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#define STM32_NGTIMNDMA 0 /* No general timers without DMA */
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#if defined(CONFIG_STM32_STM32WB30) || defined(CONFIG_STM32_STM32WB50) \
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|| defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55)
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# define STM32_NGTIM16 2 /* 16-bit general timers TIM16-17 with DMA */
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#else
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# define STM32_NGTIM16 0 /* No 16-bit general timers */
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#endif
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#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55)
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# define STM32_NDMA 2 /* DMA1-2 with 7 channels each */
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# define STM32_NI2S 1 /* SAI1 (dual channel high quality audio) */
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# define STM32_NI2C 2 /* I2C1, I2C3 */
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# define STM32_NUSBOTG 1 /* USB 2.0 FS */
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# define STM32_NCMP 2 /* Two Comparators */
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# if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V)
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# define STM32_NSPI 3 /* SPI1-2, QSPI */
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# else
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# define STM32_NSPI 2 /* SPI1, QSPI */
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# endif
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#else
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# define STM32_NDMA 1 /* DMA1 with 7 channels */
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# define STM32_NI2S 0 /* No SAI */
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# define STM32_NI2C 1 /* I2C1 */
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# define STM32_NUSBOTG 0 /* No USB */
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# define STM32_NCMP 0 /* No Comparators */
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# define STM32_NSPI 1 /* SPI1 */
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#endif
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#if defined(CONFIG_STM32_STM32WB15) || defined(CONFIG_STM32_STM32WB35) \
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|| defined(CONFIG_STM32_STM32WB55)
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# define STM32_NLPUART 1 /* LPUART1 */
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#else
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# define STM32_NLPUART 0 /* No LPUART */
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#endif
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#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V)
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# define STM32_NCAPSENSE 18 /* Capacitive sensing channels */
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#else
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# define STM32_NCAPSENSE 0 /* No Capacitive sensing */
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#endif
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#if defined(CONFIG_STM32_STM32WB55)
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# define STM32_NLCD 1 /* One LCD controller with up to 8x40
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* terminals, depending on subfamily.
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* 55Cx: 4x13
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* 55Rx: 4x28
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* 55Vx: 4x44, 8x40 */
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#else
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# define STM32_NLCD 0 /* No LCD */
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#endif
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#define STM32_NUSART 1 /* USART1 */
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#define STM32_NCAN 0 /* No CAN */
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#define STM32_NSDIO 0 /* No SDIO interface */
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#define STM32_NADC 1 /* ADC1, up to 19-channels */
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#define STM32_NDAC 0 /* No DAC */
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#define STM32_NCRC 1 /* CRC */
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#define STM32_NETHERNET 0 /* No ethernet */
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#define STM32_NRNG 1 /* Random number generator (RNG) */
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#define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#if defined(CONFIG_STM32WB_IO_CONFIG_C)
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# define STM32_NGPIO 30 /* GPIO[A,B,C,E,H] */
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#elif defined(CONFIG_STM32WB_IO_CONFIG_C_48E)
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# define STM32_NGPIO 37 /* GPIO[A,B,C,E,H] */
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#elif defined(CONFIG_STM32WB_IO_CONFIG_C_49)
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# define STM32_NGPIO 25 /* GPIO[A,B,C,H] */
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#elif defined(CONFIG_STM32WB_IO_CONFIG_R)
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# define STM32_NGPIO 49 /* GPIO[A,B,C,D,E,H] */
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#elif defined(CONFIG_STM32WB_IO_CONFIG_V)
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# define STM32_NGPIO 72 /* GPIO[A,B,C,D,E,H] */
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#else
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# error "Unsupported STM32WB chip"
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#endif
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/* STM32WB1xCC have 48 Kib:
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* 1) 12 KiB of SRAM1 beginning at address 0x2000:0000 - 0x2000:3000
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* 2) 32 KiB of SRAM2a beginning at address 0x2003:0000 - 0x2003:8000
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* 3) 4 KiB of SRAM2b beginning at address 0x2003:8000 - 0x2003:9000
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*
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* STM32WB3xxx have 96 Kib:
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*
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* 1) 32 KiB of SRAM1 beginning at address 0x2000:0000 - 0x2000:8000
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* 2) 32 KiB of SRAM2a beginning at address 0x2003:0000 - 0x2003:8000
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* 3) 32 KiB of SRAM2b beginning at address 0x2003:8000 - 0x2004:0000
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*
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* STM32WB50CG and STM32WB55xC have 128 Kib:
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*
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* 1) 64 KiB of SRAM1 beginning at address 0x2000:0000 - 0x2001:0000
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* 2) 32 KiB of SRAM2a beginning at address 0x2003:0000 - 0x2003:8000
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* 3) 32 KiB of SRAM2b beginning at address 0x2003:8000 - 0x2004:0000
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*
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* STM32WB55x[E,Y,G] have 256 Kib:
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*
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* 1) 192 KiB of SRAM1 beginning at address 0x2000:0000 - 0x2001:8000
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* 2) 32 KiB of SRAM2a beginning at address 0x2003:0000 - 0x2003:8000
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* 3) 32 KiB of SRAM2b beginning at address 0x2003:8000 - 0x2004:0000
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*/
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#if defined(CONFIG_STM32_STM32WB10) || defined(CONFIG_STM32_STM32WB15)
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# define STM32_SRAM1_SIZE (12*1024)
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# define STM32_SRAM2A_SIZE (32*1024)
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# define STM32_SRAM2B_SIZE (4*1024)
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#elif defined(CONFIG_STM32_STM32WB30) || defined(CONFIG_STM32_STM32WB35)
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# define STM32_SRAM1_SIZE (32*1024)
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# define STM32_SRAM2A_SIZE (32*1024)
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# define STM32_SRAM2B_SIZE (32*1024)
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#elif (defined(CONFIG_STM32_STM32WB50) || defined(CONFIG_STM32_STM32WB55)) \
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&& defined(CONFIG_STM32WB_IO_CONFIG_C)
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# define STM32_SRAM1_SIZE (64*1024)
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# define STM32_SRAM2A_SIZE (32*1024)
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# define STM32_SRAM2B_SIZE (32*1024)
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#elif defined(CONFIG_STM32_STM32WB55) && \
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(defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V))
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# define STM32_SRAM1_SIZE (192*1024)
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# define STM32_SRAM2A_SIZE (32*1024)
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# define STM32_SRAM2B_SIZE (32*1024)
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#else
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# error "Unsupported STM32WB chip"
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#endif
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/* NVIC priority levels *****************************************************/
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/* 16 Programmable interrupt levels */
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#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */
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#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
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#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */
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#endif /* __ARCH_ARM_INCLUDE_STM32WB_CHIP_H */
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