mirror of
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6cda2fcc96
BREAKING CHANGE: Part of splitting the legacy stm32 super-directory; relocates the stm32f4 sources, headers and boards into arch/arm/src/stm32f4, arch/arm/include/stm32f4 and boards/arm/stm32f4. Signed-off-by: raiden00pl <raiden00@railab.me>
864 lines
56 KiB
C
864 lines
56 KiB
C
/****************************************************************************
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* arch/arm/include/stm32f4/chip.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_STM32F4_CHIP_H
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#define __ARCH_ARM_INCLUDE_STM32F4_CHIP_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Prototypes
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****************************************************************************/
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/* Get customizations for each supported chip and provide alternate function
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* pin-mapping
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*
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* NOTE: Each GPIO pin may serve either for general purpose I/O or for a
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* special alternate function (such as USART, CAN, USB, SDIO, etc.). That
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* particular pin-mapping will depend on the package and STM32 family. If
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* you are incorporating a new STM32 chip into NuttX, you will need to add
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* the pin-mapping to a header file and to include that header file below.
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* The chip-specific pin-mapping is defined in the chip datasheet.
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*/
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#if defined(CONFIG_ARCH_CHIP_STM32F401CB) || defined(CONFIG_ARCH_CHIP_STM32F401RB) || \
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defined(CONFIG_ARCH_CHIP_STM32F401VB) || defined(CONFIG_ARCH_CHIP_STM32F401CC) || \
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defined(CONFIG_ARCH_CHIP_STM32F401RC) || defined(CONFIG_ARCH_CHIP_STM32F401VC)
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# define STM32_NFSMC 0 /* No FSMC */
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# define STM32_NATIM 1 /* One advanced timers TIM1 */
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# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
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* 32-bit general timers TIM2 and 5 with DMA */
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# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
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# define STM32_NBTIM 0 /* No basic timers */
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# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/
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# define STM32_NSPI 3 /* SPI1-3 */
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# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */
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# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */
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# define STM32_NLPUART 0 /* No LPUART */
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# define STM32_NI2C 3 /* I2C1-3 */
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# define STM32_NCAN 0 /* No CAN */
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# if defined(CONFIG_ARCH_CHIP_STM32F401CB) || defined(CONFIG_ARCH_CHIP_STM32F401CC)
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# define STM32_NSDIO 0 /* No SDIO interface */
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# else
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# define STM32_NSDIO 1 /* One SDIO interface */
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# endif
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBOTG 1 /* USB OTG FS (only) */
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# define STM32_NGPIO 50 /* GPIOA-H */
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# define STM32_NADC 1 /* One 12-bit ADC1, 10 or 16 channels */
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# define STM32_NDAC 0 /* No DAC */
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# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32_NCRC 1 /* No CRC */
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# define STM32_NETHERNET 0 /* No Ethernet MAC */
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# define STM32_NRNG 0 /* No Random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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/* STM32F01xD/E Family Differences:
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*
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* PART PACKAGE FLASH SDIO ADC Channels
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* ----------- ---------------- ----- ---- ------------
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* STM32F401CD WLCSP49/UFQFPN48 384Kb No 10
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* STM32F401RD LQFP64 384Kb Yes 16
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* STM32F401VD UFBGA100/LQFP100 384Kb Yes 16
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* STM32F401CE WLCSP49/UFQFPN48 512Kb No 10
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* STM32F401RE LQFP64 512Kb Yes 16
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* STM32F401VE UFBGA100/LQFP100 512Kb Yes 16
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*/
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#elif defined(CONFIG_ARCH_CHIP_STM32F401CD) || defined(CONFIG_ARCH_CHIP_STM32F401RD) || \
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defined(CONFIG_ARCH_CHIP_STM32F401VD) || defined(CONFIG_ARCH_CHIP_STM32F401CE) || \
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defined(CONFIG_ARCH_CHIP_STM32F401RE) || defined(CONFIG_ARCH_CHIP_STM32F401VE)
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# define STM32_NFSMC 0 /* No FSMC */
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# define STM32_NATIM 1 /* One advanced timers TIM1 */
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# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
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* 32-bit general timers TIM2 and 5 with DMA */
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# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
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# define STM32_NBTIM 0 /* No basic timers */
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# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/
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# define STM32_NSPI 4 /* SPI1-4 */
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# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */
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# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */
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# define STM32_NLPUART 0 /* No LPUART */
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# define STM32_NI2C 3 /* I2C1-3 */
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# define STM32_NCAN 0 /* No CAN */
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# if defined(CONFIG_ARCH_CHIP_STM32F401CD) || defined(CONFIG_ARCH_CHIP_STM32F401CE)
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# define STM32_NSDIO 0 /* No SDIO interface */
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# else
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# define STM32_NSDIO 1 /* One SDIO interface */
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# endif
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBOTG 1 /* USB OTG FS (only) */
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# define STM32_NGPIO 50 /* GPIOA-H */
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# define STM32_NADC 1 /* One 12-bit ADC1, 10 or 16 channels */
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# define STM32_NDAC 0 /* No DAC */
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# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32_NCRC 1 /* No CRC */
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# define STM32_NETHERNET 0 /* No Ethernet MAC */
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# define STM32_NRNG 0 /* No Random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32F410RB) /* LQFP64 package, 512Kb FLASH, 96KiB SRAM */
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# define STM32_NFSMC 0 /* No FSMC */
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# define STM32_NATIM 1 /* One advanced timers TIM1 */
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# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
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* 32-bit general timers TIM2 and 5 with DMA */
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# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
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# define STM32_NBTIM 0 /* No basic timers */
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# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/
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# define STM32_NSPI 3 /* SPI1-4 */
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# define STM32_NI2S 0 /* I2S1-2 (multiplexed with SPI2-3) */
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# define STM32_NUSART 3 /* Actually only 3: USART1, 2 and 6 */
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# define STM32_NLPUART 0 /* No LPUART */
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# define STM32_NI2C 3 /* I2C1-3 */
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# define STM32_NCAN 0 /* No CAN */
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# define STM32_NSDIO 0 /* One SDIO interface */
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBOTG 0 /* USB OTG FS (only) */
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# define STM32_NGPIO 50 /* GPIOA-H */
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# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */
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# define STM32_NDAC 1 /* 12-bit DAC1, 1 channel */
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# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32_NCRC 1 /* No CRC */
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# define STM32_NETHERNET 0 /* No Ethernet MAC */
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# define STM32_NRNG 1 /* No Random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32F411CE) /* LQFP64 package, 512Kb FLASH, 128KiB SRAM */
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# define STM32_NFSMC 0 /* No FSMC */
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# define STM32_NATIM 1 /* One advanced timers TIM1 */
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# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
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* 32-bit general timers TIM2 and 5 with DMA */
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# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
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# define STM32_NBTIM 0 /* No basic timers */
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# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/
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# define STM32_NSPI 5 /* SPI1-5 */
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# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
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# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */
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# define STM32_NLPUART 0 /* No LPUART */
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# define STM32_NI2C 3 /* I2C1-3 */
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# define STM32_NCAN 0 /* No CAN */
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# define STM32_NSDIO 1 /* One SDIO interface */
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBOTG 1 /* USB OTG FS (only) */
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# define STM32_NGPIO 50 /* GPIOA-H */
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# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */
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# define STM32_NDAC 0 /* No DAC */
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# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32_NCRC 1 /* No CRC */
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# define STM32_NETHERNET 0 /* No Ethernet MAC */
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# define STM32_NRNG 0 /* No Random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32F411RE) /* LQFP64 package, 512Kb FLASH, 128KiB SRAM */
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# define STM32_NFSMC 0 /* No FSMC */
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# define STM32_NATIM 1 /* One advanced timers TIM1 */
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# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
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* 32-bit general timers TIM2 and 5 with DMA */
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# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
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# define STM32_NBTIM 0 /* No basic timers */
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# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/
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# define STM32_NSPI 5 /* SPI1-5 */
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# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
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# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */
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# define STM32_NLPUART 0 /* No LPUART */
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# define STM32_NI2C 3 /* I2C1-3 */
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# define STM32_NCAN 0 /* No CAN */
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# define STM32_NSDIO 1 /* One SDIO interface */
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBOTG 1 /* USB OTG FS (only) */
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# define STM32_NGPIO 50 /* GPIOA-H */
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# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */
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# define STM32_NDAC 0 /* No DAC */
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# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32_NCRC 1 /* No CRC */
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# define STM32_NETHERNET 0 /* No Ethernet MAC */
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# define STM32_NRNG 0 /* No Random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32F411VE) /* 100 pin LQFP/BGA package, 512Kb FLASH, 128KiB SRAM */
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# define STM32_NFSMC 0 /* No FSMC */
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# define STM32_NATIM 1 /* One advanced timers TIM1 */
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# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
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* 32-bit general timers TIM2 and 5 with DMA */
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# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
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# define STM32_NBTIM 0 /* No basic timers */
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# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/
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# define STM32_NSPI 5 /* SPI1-5 */
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# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
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# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */
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# define STM32_NLPUART 0 /* No LPUART */
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# define STM32_NI2C 3 /* I2C1-3 */
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# define STM32_NCAN 0 /* No CAN */
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# define STM32_NSDIO 1 /* One SDIO interface */
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBOTG 1 /* USB OTG FS (only) */
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# define STM32_NGPIO 81 /* GPIOA-H */
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# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */
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# define STM32_NDAC 0 /* No DAC */
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# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32_NCRC 1 /* No CRC */
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# define STM32_NETHERNET 0 /* No Ethernet MAC */
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# define STM32_NRNG 0 /* No Random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32F412CE) /* UFQFPN48 package, 512Kb FLASH, 256KiB SRAM */
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# define STM32_NFSMC 1 /* FSMC */
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# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */
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# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
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* 32-bit general timers TIM2 and 5 with DMA */
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# define STM32_NGTIMNDMA 4 /* 16-bit general timers 9, 12, 13, and 14 without DMA */
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# define STM32_NBTIM 0 /* 2 basic timers TIM6 and TIM7 */
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# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/
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# define STM32_NSPI 5 /* SPI1-5 */
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# define STM32_NI2S 3 /* I2S1-3 */
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# define STM32_NUSART 4 /* USART1, 2, 3 and 6 */
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# define STM32_NLPUART 0 /* No LPUART */
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# define STM32_NI2C 3 /* I2C1-3 */
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# define STM32_NCAN 2 /* 2 CAN */
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# define STM32_NSDIO 1 /* One SDIO interface */
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBOTG 1 /* USB OTG FS (only) */
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# define STM32_NGPIO 34 /* GPIOA-B (sans PB11) and 3 Bits of C */
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# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */
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# define STM32_NDAC 0 /* No DAC */
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# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NETHERNET 0 /* No Ethernet MAC */
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# define STM32_NRNG 1 /* Random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32F412ZG) /* 144 pin LQFP package, 1MB FLASH, 256KiB SRAM */
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# define STM32_NFSMC 1 /* FSMC */
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# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */
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# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
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* 32-bit general timers TIM2 and 5 with DMA */
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# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
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# define STM32_NBTIM 2 /* 2 basic timers TIM6 and TIM7 */
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# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/
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# define STM32_NSPI 5 /* SPI1-5 */
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# define STM32_NI2S 3 /* I2S1-3 */
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# define STM32_NUSART 6 /* USART1, 2, 3 and 6 */
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# define STM32_NLPUART 0 /* No LPUART */
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# define STM32_NI2C 3 /* I2C1-3 */
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# define STM32_NCAN 2 /* 2 CAN */
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# define STM32_NSDIO 1 /* One SDIO interface */
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBOTG 1 /* USB OTG FS (only) */
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# define STM32_NGPIO 113 /* GPIOA-H */
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# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */
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# define STM32_NDAC 0 /* No DAC */
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# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NETHERNET 0 /* No Ethernet MAC */
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# define STM32_NRNG 1 /* Random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32F405RG) /* LQFP 64 10x10x1.4 1024Kb FLASH 192Kb SRAM */
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# define STM32_NFSMC 0 /* No FSMC */
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# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
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# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
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* 32-bit general timers TIM2 and 5 with DMA */
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# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
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# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
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# define STM32_NDMA 2 /* DMA1-2 */
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# define STM32_NSPI 3 /* SPI1-3 */
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# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
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# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
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# define STM32_NLPUART 0 /* No LPUART */
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# define STM32_NI2C 3 /* I2C1-3 */
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# define STM32_NCAN 2 /* CAN1-2 */
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# define STM32_NSDIO 1 /* SDIO */
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
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# define STM32_NGPIO 139 /* GPIOA-I */
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# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */
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# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */
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# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NETHERNET 0 /* No Ethernet MAC */
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# define STM32_NRNG 1 /* Random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32F405VG) /* LQFP 100 14x14x1.4 1024Kb FLASH 192Kb SRAM */
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# define STM32_NFSMC 1 /* FSMC */
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# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
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# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
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* 32-bit general timers TIM2 and 5 with DMA */
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# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
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# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
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# define STM32_NDMA 2 /* DMA1-2 */
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# define STM32_NSPI 3 /* SPI1-3 */
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# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
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# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
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# define STM32_NLPUART 0 /* No LPUART */
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# define STM32_NI2C 3 /* I2C1-3 */
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# define STM32_NCAN 2 /* CAN1-2 */
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# define STM32_NSDIO 1 /* SDIO */
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
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# define STM32_NGPIO 139 /* GPIOA-I */
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# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */
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# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */
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# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NETHERNET 0 /* No Ethernet MAC */
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# define STM32_NRNG 1 /* Random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32F405ZG) /* LQFP 144 20x20x1.4 1024Kb FLASH 192Kb SRAM */
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# define STM32_NFSMC 1 /* FSMC */
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# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
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# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
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* 32-bit general timers TIM2 and 5 with DMA */
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# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
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# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
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# define STM32_NDMA 2 /* DMA1-2 */
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|
# define STM32_NSPI 3 /* SPI1-3 */
|
|
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
|
|
# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
|
|
# define STM32_NLPUART 0 /* No LPUART */
|
|
# define STM32_NI2C 3 /* I2C1-3 */
|
|
# define STM32_NCAN 2 /* CAN1-2 */
|
|
# define STM32_NSDIO 1 /* SDIO */
|
|
# define STM32_NLCD 0 /* No LCD */
|
|
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
|
|
# define STM32_NGPIO 139 /* GPIOA-I */
|
|
# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
|
|
# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */
|
|
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
|
|
# define STM32_NCRC 1 /* CRC */
|
|
# define STM32_NETHERNET 0 /* No Ethernet MAC */
|
|
# define STM32_NRNG 1 /* Random number generator (RNG) */
|
|
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_STM32F407VE) /* LQFP-100 512Kb FLASH 192Kb SRAM */
|
|
# define STM32_NFSMC 1 /* FSMC */
|
|
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
|
|
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
|
|
* 32-bit general timers TIM2 and 5 with DMA */
|
|
# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
|
|
# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
|
|
# define STM32_NDMA 2 /* DMA1-2 */
|
|
# define STM32_NSPI 3 /* SPI1-3 */
|
|
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
|
|
# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
|
|
# define STM32_NLPUART 0 /* No LPUART */
|
|
# define STM32_NI2C 3 /* I2C1-3 */
|
|
# define STM32_NCAN 2 /* CAN1-2 */
|
|
# define STM32_NSDIO 1 /* SDIO */
|
|
# define STM32_NLCD 0 /* No LCD */
|
|
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
|
|
# define STM32_NGPIO 139 /* GPIOA-I */
|
|
# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */
|
|
# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */
|
|
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
|
|
# define STM32_NCRC 1 /* CRC */
|
|
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
|
|
# define STM32_NRNG 1 /* Random number generator (RNG) */
|
|
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_STM32F407VG) /* LQFP-100 14x14x1.4 1024Kb FLASH 192Kb SRAM */
|
|
# define STM32_NFSMC 1 /* FSMC */
|
|
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
|
|
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
|
|
* 32-bit general timers TIM2 and 5 with DMA */
|
|
# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
|
|
# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
|
|
# define STM32_NDMA 2 /* DMA1-2 */
|
|
# define STM32_NSPI 3 /* SPI1-3 */
|
|
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
|
|
# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
|
|
# define STM32_NLPUART 0 /* No LPUART */
|
|
# define STM32_NI2C 3 /* I2C1-3 */
|
|
# define STM32_NCAN 2 /* CAN1-2 */
|
|
# define STM32_NSDIO 1 /* SDIO */
|
|
# define STM32_NLCD 0 /* No LCD */
|
|
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
|
|
# define STM32_NGPIO 139 /* GPIOA-I */
|
|
# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */
|
|
# define STM32_NDAC 1 /* 12-bit DAC1, 1 channel */
|
|
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
|
|
# define STM32_NCRC 1 /* CRC */
|
|
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
|
|
# define STM32_NRNG 1 /* Random number generator (RNG) */
|
|
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_STM32F407ZE) /* LQFP-144 512Kb FLASH 192Kb SRAM */
|
|
# define STM32_NFSMC 1 /* FSMC */
|
|
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
|
|
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
|
|
* 32-bit general timers TIM2 and 5 with DMA */
|
|
# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
|
|
# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
|
|
# define STM32_NDMA 2 /* DMA1-2 */
|
|
# define STM32_NSPI 3 /* SPI1-3 */
|
|
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
|
|
# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
|
|
# define STM32_NLPUART 0 /* No LPUART */
|
|
# define STM32_NI2C 3 /* I2C1-3 */
|
|
# define STM32_NCAN 2 /* CAN1-2 */
|
|
# define STM32_NSDIO 1 /* SDIO */
|
|
# define STM32_NLCD 0 /* No LCD */
|
|
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
|
|
# define STM32_NGPIO 139 /* GPIOA-I */
|
|
# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
|
|
# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */
|
|
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
|
|
# define STM32_NCRC 1 /* CRC */
|
|
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
|
|
# define STM32_NRNG 1 /* Random number generator (RNG) */
|
|
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_STM32F407ZG) /* LQFP 144 20x20x1.4 1024Kb FLASH 192Kb SRAM */
|
|
# define STM32_NFSMC 1 /* FSMC */
|
|
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
|
|
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
|
|
* 32-bit general timers TIM2 and 5 with DMA */
|
|
# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
|
|
# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
|
|
# define STM32_NDMA 2 /* DMA1-2 */
|
|
# define STM32_NSPI 3 /* SPI1-3 */
|
|
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
|
|
# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
|
|
# define STM32_NLPUART 0 /* No LPUART */
|
|
# define STM32_NI2C 3 /* I2C1-3 */
|
|
# define STM32_NCAN 2 /* CAN1-2 */
|
|
# define STM32_NSDIO 1 /* SDIO */
|
|
# define STM32_NLCD 0 /* No LCD */
|
|
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
|
|
# define STM32_NGPIO 139 /* GPIOA-I */
|
|
# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
|
|
# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */
|
|
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
|
|
# define STM32_NCRC 1 /* CRC */
|
|
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
|
|
# define STM32_NRNG 1 /* Random number generator (RNG) */
|
|
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_STM32F407IE) /* LQFP 176 24x24x1.4 512Kb FLASH 192Kb SRAM */
|
|
# define STM32_NFSMC 1 /* FSMC */
|
|
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
|
|
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
|
|
* 32-bit general timers TIM2 and 5 with DMA */
|
|
# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
|
|
# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
|
|
# define STM32_NDMA 2 /* DMA1-2 */
|
|
# define STM32_NSPI 3 /* SPI1-3 */
|
|
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
|
|
# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 (?) */
|
|
# define STM32_NLPUART 0 /* No LPUART */
|
|
# define STM32_NI2C 3 /* I2C1-3 */
|
|
# define STM32_NCAN 2 /* CAN1-2 */
|
|
# define STM32_NSDIO 1 /* SDIO */
|
|
# define STM32_NLCD 0 /* No LCD */
|
|
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
|
|
# define STM32_NGPIO 139 /* GPIOA-I */
|
|
# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
|
|
# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */
|
|
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
|
|
# define STM32_NCRC 1 /* CRC */
|
|
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
|
|
# define STM32_NRNG 1 /* Random number generator (RNG) */
|
|
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_STM32F407IG) /* BGA 176; LQFP 176 24x24x1.4 1024Kb FLASH 192Kb SRAM */
|
|
# define STM32_NFSMC 1 /* FSMC */
|
|
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
|
|
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
|
|
* 32-bit general timers TIM2 and 5 with DMA */
|
|
# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
|
|
# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
|
|
# define STM32_NDMA 2 /* DMA1-2 */
|
|
# define STM32_NSPI 3 /* SPI1-3 */
|
|
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
|
|
# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
|
|
# define STM32_NLPUART 0 /* No LPUART */
|
|
# define STM32_NI2C 3 /* I2C1-3 */
|
|
# define STM32_NCAN 2 /* CAN1-2 */
|
|
# define STM32_NSDIO 1 /* SDIO */
|
|
# define STM32_NLCD 0 /* No LCD */
|
|
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
|
|
# define STM32_NGPIO 139 /* GPIOA-I */
|
|
# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
|
|
# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */
|
|
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
|
|
# define STM32_NCRC 1 /* CRC */
|
|
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
|
|
# define STM32_NRNG 1 /* Random number generator (RNG) */
|
|
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_STM32F427I) /* BGA176; LQFP176 1024/2048KiB flash 256KiB SRAM */
|
|
# define STM32_NFSMC 1 /* FSMC */
|
|
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
|
|
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
|
|
* 32-bit general timers TIM2 and 5 with DMA */
|
|
# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
|
|
# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
|
|
# define STM32_NDMA 2 /* DMA1-2 */
|
|
# define STM32_NSPI 6 /* SPI1-6 */
|
|
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
|
|
# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */
|
|
# define STM32_NLPUART 0 /* No LPUART */
|
|
# define STM32_NI2C 3 /* I2C1-3 */
|
|
# define STM32_NCAN 2 /* CAN1-2 */
|
|
# define STM32_NSDIO 1 /* SDIO */
|
|
# define STM32_NLCD 0 /* No LCD */
|
|
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
|
|
# define STM32_NGPIO 139 /* GPIOA-I */
|
|
# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
|
|
# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */
|
|
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
|
|
# define STM32_NCRC 1 /* CRC */
|
|
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
|
|
# define STM32_NRNG 1 /* Random number generator (RNG) */
|
|
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_STM32F427Z) /* LQFP144 1024/2048KiB flash 256KiB SRAM */
|
|
# define STM32_NFSMC 1 /* FSMC */
|
|
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
|
|
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
|
|
* 32-bit general timers TIM2 and 5 with DMA */
|
|
# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
|
|
# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
|
|
# define STM32_NDMA 2 /* DMA1-2 */
|
|
# define STM32_NSPI 6 /* SPI1-6 */
|
|
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
|
|
# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */
|
|
# define STM32_NLPUART 0 /* No LPUART */
|
|
# define STM32_NI2C 3 /* I2C1-3 */
|
|
# define STM32_NCAN 2 /* CAN1-2 */
|
|
# define STM32_NSDIO 1 /* SDIO */
|
|
# define STM32_NLCD 0 /* No LCD */
|
|
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
|
|
# define STM32_NGPIO 139 /* GPIOA-I */
|
|
# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
|
|
# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */
|
|
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
|
|
# define STM32_NCRC 1 /* CRC */
|
|
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
|
|
# define STM32_NRNG 1 /* Random number generator (RNG) */
|
|
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_STM32F427V) /* LQFP100 1024/2048KiB flash 256KiB SRAM */
|
|
# define STM32_NFSMC 1 /* FSMC */
|
|
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
|
|
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
|
|
* 32-bit general timers TIM2 and 5 with DMA */
|
|
# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
|
|
# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
|
|
# define STM32_NDMA 2 /* DMA1-2 */
|
|
# define STM32_NSPI 4 /* SPI1-4 */
|
|
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
|
|
# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */
|
|
# define STM32_NLPUART 0 /* No LPUART */
|
|
# define STM32_NI2C 3 /* I2C1-3 */
|
|
# define STM32_NCAN 2 /* CAN1-2 */
|
|
# define STM32_NSDIO 1 /* SDIO */
|
|
# define STM32_NLCD 0 /* No LCD */
|
|
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
|
|
# define STM32_NGPIO 139 /* GPIOA-I */
|
|
# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
|
|
# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */
|
|
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
|
|
# define STM32_NCRC 1 /* CRC */
|
|
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
|
|
# define STM32_NRNG 1 /* Random number generator (RNG) */
|
|
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_STM32F429I) /* BGA176; LQFP176 1024/2048KiB flash 256KiB SRAM */
|
|
# define STM32_NFSMC 1 /* FSMC */
|
|
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
|
|
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
|
|
* 32-bit general timers TIM2 and 5 with DMA */
|
|
# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
|
|
# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
|
|
# define STM32_NDMA 2 /* DMA1-2 */
|
|
# define STM32_NSPI 6 /* SPI1-6 */
|
|
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
|
|
# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */
|
|
# define STM32_NLPUART 0 /* No LPUART */
|
|
# define STM32_NI2C 3 /* I2C1-3 */
|
|
# define STM32_NCAN 2 /* CAN1-2 */
|
|
# define STM32_NSDIO 1 /* SDIO */
|
|
# define STM32_NLCD 0 /* No LCD */
|
|
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
|
|
# define STM32_NGPIO 139 /* GPIOA-I */
|
|
# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
|
|
# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */
|
|
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
|
|
# define STM32_NCRC 1 /* CRC */
|
|
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
|
|
# define STM32_NRNG 1 /* Random number generator (RNG) */
|
|
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_STM32F429Z) /* LQFP144 1024/2048KiB flash 256KiB SRAM */
|
|
# define STM32_NFSMC 1 /* FSMC */
|
|
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
|
|
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
|
|
* 32-bit general timers TIM2 and 5 with DMA */
|
|
# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
|
|
# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
|
|
# define STM32_NDMA 2 /* DMA1-2 */
|
|
# define STM32_NSPI 6 /* SPI1-6 */
|
|
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
|
|
# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */
|
|
# define STM32_NLPUART 0 /* No LPUART */
|
|
# define STM32_NI2C 3 /* I2C1-3 */
|
|
# define STM32_NCAN 2 /* CAN1-2 */
|
|
# define STM32_NSDIO 1 /* SDIO */
|
|
# define STM32_NLCD 0 /* No LCD */
|
|
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
|
|
# define STM32_NGPIO 139 /* GPIOA-I */
|
|
# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
|
|
# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */
|
|
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
|
|
# define STM32_NCRC 1 /* CRC */
|
|
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
|
|
# define STM32_NRNG 1 /* Random number generator (RNG) */
|
|
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_STM32F429V) /* LQFP100 1024/2048KiB flash 256KiB SRAM */
|
|
# define STM32_NFSMC 1 /* FSMC */
|
|
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
|
|
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
|
|
* 32-bit general timers TIM2 and 5 with DMA */
|
|
# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
|
|
# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
|
|
# define STM32_NDMA 2 /* DMA1-2 */
|
|
# define STM32_NSPI 4 /* SPI1-4 */
|
|
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
|
|
# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */
|
|
# define STM32_NLPUART 0 /* No LPUART */
|
|
# define STM32_NI2C 3 /* I2C1-3 */
|
|
# define STM32_NCAN 2 /* CAN1-2 */
|
|
# define STM32_NSDIO 1 /* SDIO */
|
|
# define STM32_NLCD 0 /* No LCD */
|
|
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
|
|
# define STM32_NGPIO 139 /* GPIOA-I */
|
|
# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
|
|
# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */
|
|
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
|
|
# define STM32_NCRC 1 /* CRC */
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|
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
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|
# define STM32_NRNG 1 /* Random number generator (RNG) */
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|
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
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|
|
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#elif defined(CONFIG_ARCH_CHIP_STM32F446M) /* WLCSP81 256/512KiB flash 128KiB SRAM */
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|
# define STM32_NFSMC 0 /* FSMC */
|
|
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
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|
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
|
|
* 32-bit general timers TIM2 and 5 with DMA */
|
|
# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
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|
# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
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|
# define STM32_NDMA 2 /* DMA1-2 */
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|
# define STM32_NSPI 4 /* SPI1-4 */
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|
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
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|
# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
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|
# define STM32_NLPUART 0 /* No LPUART */
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|
# define STM32_NI2C 3 /* I2C1-3 */
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|
# define STM32_NCAN 2 /* CAN1-2 */
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|
# define STM32_NSDIO 1 /* SDIO */
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|
# define STM32_NLCD 0 /* No LCD */
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|
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
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|
# define STM32_NGPIO 114 /* GPIOA-I */
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|
# define STM32_NADC 2 /* 12-bit ADC1-3, 14 channels */
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|
# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */
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|
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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|
# define STM32_NCRC 1 /* CRC */
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|
# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */
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|
# define STM32_NRNG 0 /* Random number generator (RNG) */
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|
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
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|
|
|
#elif defined(CONFIG_ARCH_CHIP_STM32F446R) /* LQFP64 256/512KiB flash 128KiB SRAM */
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|
# define STM32_NFSMC 0 /* FSMC */
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|
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
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|
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
|
|
* 32-bit general timers TIM2 and 5 with DMA */
|
|
# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
|
|
# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
|
|
# define STM32_NDMA 2 /* DMA1-2 */
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|
# define STM32_NSPI 4 /* SPI1-4 */
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|
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
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|
# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
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|
# define STM32_NLPUART 0 /* No LPUART */
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|
# define STM32_NI2C 3 /* I2C1-3 */
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|
# define STM32_NCAN 2 /* CAN1-2 */
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|
# define STM32_NSDIO 1 /* SDIO */
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|
# define STM32_NLCD 0 /* No LCD */
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|
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
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|
# define STM32_NGPIO 114 /* GPIOA-I */
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|
# define STM32_NADC 2 /* 12-bit ADC1-3, 16 channels */
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|
# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */
|
|
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
|
|
# define STM32_NCRC 1 /* CRC */
|
|
# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */
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|
# define STM32_NRNG 0 /* Random number generator (RNG) */
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|
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
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|
|
|
#elif defined(CONFIG_ARCH_CHIP_STM32F446V) /* LQFP100 256/512KiB flash 128KiB SRAM */
|
|
# define STM32_NFSMC 1 /* FSMC */
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|
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
|
|
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
|
|
* 32-bit general timers TIM2 and 5 with DMA */
|
|
# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
|
|
# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
|
|
# define STM32_NDMA 2 /* DMA1-2 */
|
|
# define STM32_NSPI 4 /* SPI1-4 */
|
|
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
|
|
# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
|
|
# define STM32_NLPUART 0 /* No LPUART */
|
|
# define STM32_NI2C 3 /* I2C1-3 */
|
|
# define STM32_NCAN 2 /* CAN1-2 */
|
|
# define STM32_NSDIO 1 /* SDIO */
|
|
# define STM32_NLCD 0 /* No LCD */
|
|
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
|
|
# define STM32_NGPIO 114 /* GPIOA-I */
|
|
# define STM32_NADC 2 /* 12-bit ADC1-3, 16 channels */
|
|
# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */
|
|
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
|
|
# define STM32_NCRC 1 /* CRC */
|
|
# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */
|
|
# define STM32_NRNG 0 /* Random number generator (RNG) */
|
|
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_STM32F446Z) /* LQFP144 UFBGA144 256/512KiB flash 128KiB SRAM */
|
|
# define STM32_NFSMC 1 /* FSMC */
|
|
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
|
|
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
|
|
* 32-bit general timers TIM2 and 5 with DMA */
|
|
# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
|
|
# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
|
|
# define STM32_NDMA 2 /* DMA1-2 */
|
|
# define STM32_NSPI 4 /* SPI1-4 */
|
|
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
|
|
# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
|
|
# define STM32_NLPUART 0 /* No LPUART */
|
|
# define STM32_NI2C 3 /* I2C1-3 */
|
|
# define STM32_NCAN 2 /* CAN1-2 */
|
|
# define STM32_NSDIO 1 /* SDIO */
|
|
# define STM32_NLCD 0 /* No LCD */
|
|
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
|
|
# define STM32_NGPIO 114 /* GPIOA-I */
|
|
# define STM32_NADC 2 /* 12-bit ADC1-3, 16 channels */
|
|
# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */
|
|
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
|
|
# define STM32_NCRC 1 /* CRC */
|
|
# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */
|
|
# define STM32_NRNG 0 /* Random number generator (RNG) */
|
|
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_STM32F429N) /* TFBGA216 1024/2048KiB flash 256KiB SRAM */
|
|
# define STM32_NFSMC 1 /* FSMC */
|
|
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
|
|
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
|
|
* 32-bit general timers TIM2 and 5 with DMA */
|
|
# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
|
|
# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
|
|
# define STM32_NDMA 2 /* DMA1-2 */
|
|
# define STM32_NSPI 6 /* SPI1-6 */
|
|
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
|
|
# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */
|
|
# define STM32_NLPUART 0 /* No LPUART */
|
|
# define STM32_NI2C 3 /* I2C1-3 */
|
|
# define STM32_NCAN 2 /* CAN1-2 */
|
|
# define STM32_NSDIO 1 /* SDIO */
|
|
# define STM32_NLCD 0 /* No LCD */
|
|
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
|
|
# define STM32_NGPIO 168 /* GPIOA-K */
|
|
# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
|
|
# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */
|
|
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
|
|
# define STM32_NCRC 1 /* CRC */
|
|
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
|
|
# define STM32_NRNG 1 /* Random number generator (RNG) */
|
|
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_STM32F469A) || \
|
|
defined(CONFIG_ARCH_CHIP_STM32F469I) || \
|
|
defined(CONFIG_ARCH_CHIP_STM32F469B) || \
|
|
defined(CONFIG_ARCH_CHIP_STM32F469N)
|
|
# define STM32_NFSMC 1 /* FSMC */
|
|
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
|
|
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
|
|
* 32-bit general timers TIM2 and 5 with DMA */
|
|
# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
|
|
# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
|
|
# define STM32_NDMA 2 /* DMA1-2 */
|
|
# define STM32_NSPI 6 /* SPI1-6 */
|
|
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
|
|
# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */
|
|
# define STM32_NLPUART 0 /* No LPUART */
|
|
# define STM32_NI2C 3 /* I2C1-3 */
|
|
# define STM32_NCAN 2 /* CAN1-2 */
|
|
# define STM32_NSDIO 1 /* SDIO */
|
|
# define STM32_NLCD 1 /* LCD */
|
|
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
|
|
# if defined(CONFIG_ARCH_CHIP_STM32F469A)
|
|
# define STM32_NGPIO 114 /* GPIOA-I */
|
|
# elif defined(CONFIG_ARCH_CHIP_STM32F469I)
|
|
# define STM32_NGPIO 131 /* GPIOA-I */
|
|
# elif defined(CONFIG_ARCH_CHIP_STM32F469B) || \
|
|
defined(CONFIG_ARCH_CHIP_STM32F469N)
|
|
# define STM32_NGPIO 161 /* GPIOA-K */
|
|
# endif
|
|
# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
|
|
# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */
|
|
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
|
|
# define STM32_NCRC 1 /* CRC */
|
|
# if defined(CONFIG_ARCH_CHIP_STM32F469A)
|
|
# define STM32_NETHERNET 0 /* No Ethernet MAC */
|
|
# elif defined(CONFIG_ARCH_CHIP_STM32F469I) || \
|
|
defined(CONFIG_ARCH_CHIP_STM32F469B) || \
|
|
defined(CONFIG_ARCH_CHIP_STM32F469N)
|
|
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
|
|
# endif
|
|
# define STM32_NRNG 1 /* Random number generator (RNG) */
|
|
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
|
|
|
|
#else
|
|
# error "Unsupported STM32 chip"
|
|
#endif
|
|
|
|
/* Peripheral IP versions ***************************************************/
|
|
|
|
/* Peripheral IP versions are invariant and should be decided here, not in
|
|
* Kconfig.
|
|
*
|
|
* REVISIT: Currently only SPI IP version is handled here, with others being
|
|
* handled in Kconfig. Those others need to be gradually refactored
|
|
* and resolved here.
|
|
*/
|
|
|
|
#define STM32_HAVE_IP_SPI_V2
|
|
|
|
/* NVIC priority levels *****************************************************/
|
|
|
|
#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */
|
|
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
|
|
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
|
|
#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */
|
|
|
|
#endif /* __ARCH_ARM_INCLUDE_STM32F4_CHIP_H */
|