mirror of
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e21a15eb4e
BREAKING CHANGE: Part of splitting the legacy stm32 super-directory; relocates the stm32f1 sources, headers and boards into arch/arm/src/stm32f1, arch/arm/include/stm32f1 and boards/arm/stm32f1. Signed-off-by: raiden00pl <raiden00@railab.me>
495 lines
28 KiB
C
495 lines
28 KiB
C
/****************************************************************************
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* arch/arm/include/stm32f1/chip.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_STM32F1_CHIP_H
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#define __ARCH_ARM_INCLUDE_STM32F1_CHIP_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Prototypes
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****************************************************************************/
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/* Get customizations for each supported chip and provide alternate function
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* pin-mapping
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*
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* NOTE: Each GPIO pin may serve either for general purpose I/O or for a
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* special alternate function (such as USART, CAN, USB, SDIO, etc.). That
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* particular pin-mapping will depend on the package and STM32 family. If
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* you are incorporating a new STM32 chip into NuttX, you will need to add
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* the pin-mapping to a header file and to include that header file below.
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* The chip-specific pin-mapping is defined in the chip datasheet.
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*/
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#if defined(CONFIG_ARCH_CHIP_STM32F100C8) || defined(CONFIG_ARCH_CHIP_STM32F100CB) \
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|| defined(CONFIG_ARCH_CHIP_STM32F100R8) || defined(CONFIG_ARCH_CHIP_STM32F100RB)
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# define STM32_NFSMC 0 /* No FSMC */
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# define STM32_NATIM 1 /* One advanced timer TIM1 */
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# define STM32_NGTIM 3 /* 16-bit general timers TIM2-4 with DMA */
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# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */
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# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */
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/* TODO: there are also 3 additional timers (15-17)
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* that don't fit any existing category
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*/
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# define STM32_NDMA 1 /* DMA1 */
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# define STM32_NSPI 2 /* SPI1-2 */
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# define STM32_NI2S 0 /* No I2S */
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# define STM32_NUSART 3 /* USART1-3 */
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# define STM32_NLPUART 0 /* No LPUART */
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# define STM32_NI2C 2 /* I2C1-2 */
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# define STM32_NCAN 0 /* No CAN */
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# define STM32_NSDIO 0 /* No SDIO */
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
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# define STM32_NGPIO 64 /* GPIOA-D */
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# define STM32_NADC 1 /* ADC1 */
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# define STM32_NDAC 2 /* DAC 1, 2 channels */
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# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC1 */
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# define STM32_NETHERNET 0 /* No Ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32F100V8) || defined(CONFIG_ARCH_CHIP_STM32F100VB)
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# define STM32_NFSMC 0 /* FSMC */
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# define STM32_NATIM 1 /* One advanced timer TIM1 */
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# define STM32_NGTIM 3 /* 16-bit general timers TIM2-4 with DMA */
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# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */
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# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */
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/* TODO: there are also 3 additional timers (15-17)
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* that don't fit any existing category
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*/
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# define STM32_NDMA 1 /* DMA1 */
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# define STM32_NSPI 2 /* SPI1-2 */
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# define STM32_NI2S 0 /* No I2S */
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# define STM32_NUSART 3 /* USART1-3 */
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# define STM32_NLPUART 0 /* No LPUART */
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# define STM32_NI2C 2 /* I2C1-2 */
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# define STM32_NCAN 0 /* No CAN */
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# define STM32_NSDIO 0 /* No SDIO */
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
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# define STM32_NGPIO 80 /* GPIOA-E */
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# define STM32_NADC 1 /* ADC1 */
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# define STM32_NDAC 2 /* DAC 1, 2 channels */
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# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC1 */
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# define STM32_NETHERNET 0 /* No Ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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/* STM32 F100 High-density value Line ***************************************/
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#elif defined(CONFIG_ARCH_CHIP_STM32F100RC) || defined(CONFIG_ARCH_CHIP_STM32F100RD) \
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|| defined(CONFIG_ARCH_CHIP_STM32F100RE)
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# define STM32_NFSMC 0 /* FSMC */
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# define STM32_NATIM 1 /* One advanced timer TIM1 */
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# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */
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# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */
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# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */
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/* TODO: there are also 6 additional timers (12-17)
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* that don't fit any existing category
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*/
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# define STM32_NDMA 2 /* DMA1-2 */
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# define STM32_NSPI 3 /* SPI1-3 */
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# define STM32_NI2S 0 /* No I2S */
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# define STM32_NUSART 5 /* USART1-5 */
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# define STM32_NLPUART 0 /* No LPUART */
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# define STM32_NI2C 2 /* I2C1-2 */
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# define STM32_NCAN 0 /* No CAN */
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# define STM32_NSDIO 0 /* No SDIO */
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
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# define STM32_NGPIO 64 /* GPIOA-D */
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# define STM32_NADC 1 /* ADC1 */
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# define STM32_NDAC 2 /* DAC 1, 2 channels */
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# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC1 */
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# define STM32_NETHERNET 0 /* No Ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32F100VC) || defined(CONFIG_ARCH_CHIP_STM32F100VD) \
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|| defined(CONFIG_ARCH_CHIP_STM32F100VE)
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# define STM32_NFSMC 1 /* FSMC */
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# define STM32_NATIM 1 /* One advanced timer TIM1 */
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# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */
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# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */
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# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */
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/* TODO: there are also 6 additional timers (12-17)
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* that don't fit any existing category
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*/
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# define STM32_NDMA 2 /* DMA1-2 */
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# define STM32_NSPI 3 /* SPI1-3 */
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# define STM32_NI2S 0 /* No I2S */
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# define STM32_NUSART 5 /* USART1-5 */
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# define STM32_NLPUART 0 /* No LPUART */
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# define STM32_NI2C 2 /* I2C1-2 */
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# define STM32_NCAN 0 /* No CAN */
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# define STM32_NSDIO 0 /* No SDIO */
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
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# define STM32_NGPIO 80 /* GPIOA-E */
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# define STM32_NADC 1 /* ADC1 */
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# define STM32_NDAC 2 /* DAC 1, 2 channels */
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# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC1 */
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# define STM32_NETHERNET 0 /* No Ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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/* STM32 F102x8/102xB Medium Density USB Access Family **********************/
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#elif defined(CONFIG_ARCH_CHIP_STM32F102CB)
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# define STM32_NFSMC 1 /* FSMC */
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# define STM32_NATIM 0 /* No advanced timer TIM1 */
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# define STM32_NGTIM 3 /* 16-bit general timers TIM2-4 */
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# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */
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# define STM32_NBTIM 0 /* No basic timers */
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# define STM32_NDMA 1 /* DMA */
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# define STM32_NSPI 2 /* SPI1-2 */
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# define STM32_NI2S 0 /* No I2S */
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# define STM32_NUSART 3 /* USART1-3 */
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# define STM32_NLPUART 0 /* No LPUART */
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# define STM32_NI2C 2 /* I2C1-2 */
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# define STM32_NCAN 0 /* No CAN */
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# define STM32_NSDIO 0 /* No SDIO */
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
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# define STM32_NGPIO 37 /* GPIOA-D */
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# define STM32_NADC 1 /* ADC1 */
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# define STM32_NDAC 0 /* No DAC */
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# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC1 */
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# define STM32_NETHERNET 0 /* No ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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/* STM32 F103 Low Density Family ********************************************/
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/* STM32F103C4 & STM32F103C6 */
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#elif defined(CONFIG_ARCH_CHIP_STM32F103C4)
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# define STM32_NFSMC 0 /* FSMC */
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# define STM32_NATIM 1 /* One advanced timer TIM1 */
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# define STM32_NGTIM 2 /* General timers TIM2,3 */
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# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */
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# define STM32_NBTIM 0 /* No basic timer */
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# define STM32_NDMA 1 /* DMA1 */
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# define STM32_NSPI 1 /* SPI1 */
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# define STM32_NI2S 0 /* No I2S */
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# define STM32_NUSART 2 /* USART1-2 */
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# define STM32_NLPUART 0 /* No LPUART */
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# define STM32_NI2C 1 /* I2C1 */
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# define STM32_NCAN 1 /* bxCAN1 */
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# define STM32_NSDIO 0 /* No SDIO */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
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# define STM32_NGPIO 37 /* GPIOA-C */
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# define STM32_NADC 2 /* ADC1-2 */
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# define STM32_NDAC 0 /* No DAC */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NETHERNET 0 /* No Ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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/* STM32 F103 Medium Density Performance Line *******************************/
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#elif defined(CONFIG_ARCH_CHIP_STM32F103T8) || defined(CONFIG_ARCH_CHIP_STM32F103TB)
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# define STM32_NFSMC 0 /* No FSMC */
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# define STM32_NATIM 1 /* One advanced timer TIM1 */
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# define STM32_NGTIM 3 /* General timers TIM2-4 */
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# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */
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# define STM32_NBTIM 0 /* No basic timers */
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# define STM32_NDMA 1 /* DMA1, 7 channels */
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# define STM32_NSPI 1 /* SPI1 */
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# define STM32_NI2S 0 /* No I2S */
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# define STM32_NUSART 2 /* USART1-2 */
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# define STM32_NLPUART 0 /* No LPUART */
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# define STM32_NI2C 1 /* I2C1 */
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# define STM32_NCAN 1 /* bxCAN1 */
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# define STM32_NSDIO 0 /* No SDIO */
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
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# define STM32_NGPIO 26 /* GPIOA-E */
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# define STM32_NADC 2 /* ADC1-2 */
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# define STM32_NDAC 0 /* No DAC */
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# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NETHERNET 0 /* No Ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32F103C8) || defined(CONFIG_ARCH_CHIP_STM32F103CB)
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# define STM32_NFSMC 0 /* No FSMC */
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# define STM32_NATIM 1 /* One advanced timer TIM1 */
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# define STM32_NGTIM 3 /* General timers TIM2-4 */
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# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */
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# define STM32_NBTIM 0 /* No basic timers */
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# define STM32_NDMA 1 /* DMA1, 7 channels */
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# define STM32_NSPI 2 /* SPI1-2 */
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# define STM32_NI2S 0 /* No I2S */
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# define STM32_NUSART 3 /* USART1-3 */
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# define STM32_NLPUART 0 /* No LPUART */
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# define STM32_NI2C 2 /* I2C1-2 */
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# define STM32_NCAN 1 /* bxCAN1 */
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# define STM32_NSDIO 0 /* No SDIO */
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
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# define STM32_NGPIO 37 /* GPIOA-C */
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# define STM32_NADC 2 /* ADC1-2 */
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# define STM32_NDAC 0 /* No DAC */
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# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NETHERNET 0 /* No Ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32F103R8) || defined(CONFIG_ARCH_CHIP_STM32F103RB)
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# define STM32_NFSMC 0 /* No FSMC */
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# define STM32_NATIM 1 /* One advanced timer TIM1 */
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# define STM32_NGTIM 3 /* General timers TIM2-4 */
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# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */
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# define STM32_NBTIM 0 /* No basic timers */
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# define STM32_NDMA 1 /* DMA1, 7 channels */
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# define STM32_NSPI 2 /* SPI1-2 */
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# define STM32_NI2S 0 /* No I2S */
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# define STM32_NUSART 3 /* USART1-3 */
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# define STM32_NLPUART 0 /* No LPUART */
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# define STM32_NI2C 2 /* I2C1-2 */
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# define STM32_NCAN 1 /* bxCAN1 */
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# define STM32_NSDIO 0 /* No SDIO */
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
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# define STM32_NGPIO 51 /* GPIOA-E */
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# define STM32_NADC 2 /* ADC1-2 */
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# define STM32_NDAC 0 /* No DAC */
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# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NETHERNET 0 /* No Ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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/* STM32 F103 High Density Family *******************************************/
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/* STM32F103RC, STM32F103RD, and STM32F103RE are all provided in 64 pin
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* packages and differ only in the available FLASH and SRAM.
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*/
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#elif defined(CONFIG_ARCH_CHIP_STM32F103RC) || defined(CONFIG_ARCH_CHIP_STM32F103RD) || \
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defined(CONFIG_ARCH_CHIP_STM32F103RE) || defined(CONFIG_ARCH_CHIP_STM32F103RG)
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# define STM32_NFSMC 1 /* FSMC */
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# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */
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# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */
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# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */
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# define STM32_NBTIM 2 /* Two basic timers TIM6 and TIM7 */
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# define STM32_NDMA 2 /* DMA1-2 */
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# define STM32_NSPI 3 /* SPI1-3 */
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# define STM32_NI2S 0 /* No I2S (?) */
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# define STM32_NUSART 5 /* USART1-5 */
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# define STM32_NLPUART 0 /* No LPUART */
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# define STM32_NI2C 2 /* I2C1-2 */
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# define STM32_NCAN 1 /* CAN1 */
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# define STM32_NSDIO 1 /* SDIO */
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
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# define STM32_NGPIO 51 /* GPIOA-D */
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# define STM32_NADC 2 /* ADC1-2 */
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# define STM32_NDAC 2 /* DAC1, 2 channels */
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# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NETHERNET 0 /* No Ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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/* STM32F103VC, STM32F103VD, and STM32F103VE are all provided in 100 pin
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* packages and differ only in the available FLASH and SRAM.
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*/
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#elif defined(CONFIG_ARCH_CHIP_STM32F103VC) || defined(CONFIG_ARCH_CHIP_STM32F103VE)
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# define STM32_NFSMC 1 /* FSMC */
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# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */
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# define STM32_NGTIM 4 /* General timers TIM2-5 */
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# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */
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# define STM32_NBTIM 2 /* Two basic timers TIM6 and TIM7 */
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# define STM32_NDMA 2 /* DMA1-2 */
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# define STM32_NSPI 3 /* SPI1-3 */
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# define STM32_NI2S 0 /* No I2S (?) */
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# define STM32_NUSART 5 /* USART1-5 */
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# define STM32_NLPUART 0 /* No LPUART */
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# define STM32_NI2C 2 /* I2C1-2 */
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# define STM32_NCAN 1 /* bxCAN1 */
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# define STM32_NSDIO 1 /* SDIO */
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
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# define STM32_NGPIO 80 /* GPIOA-E */
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# define STM32_NADC 3 /* ADC1-3 */
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# define STM32_NDAC 2 /* DAC1, 2 channels */
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# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NETHERNET 0 /* No Ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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/* STM32F103ZC, STM32F103ZD, and STM32F103ZE are all provided in 144 pin
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* packages and differ only in the available FLASH and SRAM.
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*/
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#elif defined(CONFIG_ARCH_CHIP_STM32F103ZE)
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# define STM32_NFSMC 1 /* FSMC */
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# define STM32_NATIM 1 /* One advanced timer TIM1 */
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# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */
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# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */
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|
# define STM32_NBTIM 0 /* No basic timers */
|
|
# define STM32_NDMA 2 /* DMA1-2 */
|
|
# define STM32_NSPI 3 /* SPI1-3 */
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|
# define STM32_NI2S 0 /* No I2S (?) */
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|
# define STM32_NUSART 3 /* USART1-3 */
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|
# define STM32_NLPUART 0 /* No LPUART */
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|
# define STM32_NI2C 2 /* I2C1-2 */
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|
# define STM32_NCAN 1 /* CAN1 */
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|
# define STM32_NSDIO 1 /* SDIO */
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|
# define STM32_NLCD 0 /* No LCD */
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|
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
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|
# define STM32_NGPIO 112 /* GPIOA-G */
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|
# define STM32_NADC 1 /* ADC1 */
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|
# define STM32_NDAC 0 /* No DAC */
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|
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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|
# define STM32_NCRC 0 /* No CRC */
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|
# define STM32_NETHERNET 0 /* No Ethernet */
|
|
# define STM32_NRNG 0 /* No random number generator (RNG) */
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|
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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|
|
|
/* STM32 F105/F107 Connectivity Line ****************************************/
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|
|
|
#elif defined(CONFIG_ARCH_CHIP_STM32F105VB)
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|
# define STM32_NFSMC 1 /* FSMC */
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|
# define STM32_NATIM 1 /* One advanced timers TIM1 */
|
|
# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */
|
|
# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */
|
|
# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
|
|
# define STM32_NDMA 2 /* DMA1-2 */
|
|
# define STM32_NSPI 3 /* SPI1-3 */
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|
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
|
|
# define STM32_NUSART 5 /* USART1-3, UART 4-5 */
|
|
# define STM32_NLPUART 0 /* No LPUART */
|
|
# define STM32_NI2C 2 /* I2C1-2 */
|
|
# define STM32_NCAN 2 /* CAN1-2 */
|
|
# define STM32_NSDIO 0 /* No SDIO */
|
|
# define STM32_NLCD 0 /* No LCD */
|
|
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
|
|
# define STM32_NGPIO 80 /* GPIOA-E */
|
|
# define STM32_NADC 2 /* ADC1-2 */
|
|
# define STM32_NDAC 2 /* DAC1, 2 channels */
|
|
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
|
|
# define STM32_NCRC 1 /* CRC */
|
|
# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */
|
|
# define STM32_NRNG 0 /* No random number generator (RNG) */
|
|
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_STM32F105RB)
|
|
# define STM32_NFSMC 1 /* FSMC */
|
|
# define STM32_NATIM 1 /* One advanced timers TIM1 */
|
|
# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */
|
|
# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */
|
|
# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
|
|
# define STM32_NDMA 2 /* DMA1-2 */
|
|
# define STM32_NSPI 3 /* SPI1-3 */
|
|
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
|
|
# define STM32_NUSART 5 /* USART1-3, UART 4-5 */
|
|
# define STM32_NLPUART 0 /* No LPUART */
|
|
# define STM32_NI2C 2 /* I2C1-2 */
|
|
# define STM32_NCAN 2 /* CAN1-2 */
|
|
# define STM32_NSDIO 0 /* No SDIO */
|
|
# define STM32_NLCD 0 /* No LCD */
|
|
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
|
|
# define STM32_NGPIO 51 /* GPIOA-E */
|
|
# define STM32_NADC 2 /* ADC1-2 */
|
|
# define STM32_NDAC 2 /* DAC1, 2 channels */
|
|
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
|
|
# define STM32_NCRC 1 /* CRC */
|
|
# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */
|
|
# define STM32_NRNG 0 /* No random number generator (RNG) */
|
|
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_STM32F107VC)
|
|
# define STM32_NFSMC 1 /* FSMC */
|
|
# define STM32_NATIM 1 /* One advanced timers TIM1 */
|
|
# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */
|
|
# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */
|
|
# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
|
|
# define STM32_NDMA 2 /* DMA1-2 */
|
|
# define STM32_NSPI 3 /* SPI1-3 */
|
|
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
|
|
# define STM32_NUSART 5 /* USART1-3, UART 4-5 */
|
|
# define STM32_NLPUART 0 /* No LPUART */
|
|
# define STM32_NI2C 1 /* I2C1 */
|
|
# define STM32_NCAN 2 /* CAN1-2 */
|
|
# define STM32_NSDIO 0 /* No SDIO */
|
|
# define STM32_NLCD 0 /* No LCD */
|
|
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
|
|
# define STM32_NGPIO 80 /* GPIOA-E */
|
|
# define STM32_NADC 2 /* ADC1-2*/
|
|
# define STM32_NDAC 2 /* DAC1, 2 channels */
|
|
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
|
|
# define STM32_NCRC 1 /* CRC */
|
|
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
|
|
# define STM32_NRNG 0 /* No random number generator (RNG) */
|
|
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
|
|
|
|
/* STM32 F2 Family **********************************************************/
|
|
|
|
#else
|
|
# error "Unsupported STM32 chip"
|
|
#endif
|
|
|
|
/* Peripheral IP versions ***************************************************/
|
|
|
|
/* Peripheral IP versions are invariant and should be decided here, not in
|
|
* Kconfig.
|
|
*
|
|
* REVISIT: Currently only SPI IP version is handled here, with others being
|
|
* handled in Kconfig. Those others need to be gradually refactored
|
|
* and resolved here.
|
|
*/
|
|
|
|
#define STM32_HAVE_IP_SPI_V1
|
|
|
|
/* NVIC priority levels *****************************************************/
|
|
|
|
#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */
|
|
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
|
|
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
|
|
#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */
|
|
|
|
#endif /* __ARCH_ARM_INCLUDE_STM32F1_CHIP_H */
|