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0dccc8ba21
debug.h is a NuttX-specific, non-POSIX header. Placing it in the top-level include/ directory creates naming conflicts with external projects that define their own debug.h. This commit moves the canonical header to include/nuttx/debug.h, following the NuttX convention for non-POSIX/non-standard headers, and updates all in-tree references. A backward-compatibility shim is left at include/debug.h that emits a deprecation #warning and re-includes <nuttx/debug.h>, allowing out-of-tree code to continue building while migrating. Signed-off-by: Piyush Patle <piyushpatle228@gmail.com>
192 lines
6.3 KiB
C
192 lines
6.3 KiB
C
/****************************************************************************
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* arch/xtensa/src/common/xtensa_assert.c
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <nuttx/debug.h>
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#include <assert.h>
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#include <nuttx/irq.h>
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#include <nuttx/board.h>
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#include <nuttx/syslog/syslog.h>
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#include <arch/board/board.h>
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#include "sched/sched.h"
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#include "xtensa.h"
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: xtensa_panic
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*
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* Description:
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* PANIC if an unhandled exception is received:
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*
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* - NMI exception
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* - Debug exception
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* - Double exception
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* - Kernel exception
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* - Co-processor exception
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* - High priority level2-6 Exception.
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*
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* Input Parameters:
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* xcptcode - Identifies the unhandled exception (see include/esp32/irq.h)
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* regs - The register save are at the time of the interrupt.
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*
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* Returned Value:
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* Does not return
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*
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****************************************************************************/
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void xtensa_panic(int xptcode, uint32_t *regs)
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{
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struct tcb_s **running_task = &g_running_tasks[this_cpu()];
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(*running_task)->xcp.regs = regs;
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up_set_interrupt_context(true);
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/* We get here when a un-dispatch-able, irrecoverable exception occurs */
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board_autoled_on(LED_ASSERTION);
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/* Flush any buffered SYSLOG data (from prior to the panic) */
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syslog_flush();
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_alert("Unhandled Exception %d task: %s\n", xptcode,
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get_task_name(running_task()));
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PANIC_WITH_REGS("panic", regs); /* Should not return */
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for (; ; );
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}
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/****************************************************************************
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* Name: xtensa_user
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*
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* Description:
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* PANIC if certain User Exceptions are received. All values for EXCCAUSE
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* are listed below (not all generate PANICs):
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*
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* 0 IllegalInstructionCause
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* Illegal instruction
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* 1 SyscallCause
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* SYSCALL instruction
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* 2 InstructionFetchErrorCause
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* Processor internal physical address or data error during instruction
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* fetch.
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* 3 LoadStoreErrorCause
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* Processor internal physical address or data error during load or
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* store.
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* 4 Level1InterruptCause
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* Level-1 interrupt as indicated by set level-1 bits in the INTERRUPT
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* register.
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* 5 AllocaCause
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* MOVSP instruction, if caller's registers are not in the register
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* file.
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* 6 IntegerDivideByZeroCause
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* QUOS, QUOU, REMS, or REMU divisor operand is zero.
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* 7 PCValueErrorCause Next PC Value Illegal
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* 8 PrivilegedCause
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* Attempt to execute a privileged operation when CRING != 0
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* 9 LoadStoreAlignmentCause
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* Load or store to an unaligned address.
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* 10..11 Reserved for Cadence
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* 12 InstrPIFDataErrorCause
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* PIF data error during instruction fetch.
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* 13 LoadStorePIFDataErrorCause
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* Synchronous PIF data error during LoadStore access.
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* 14 InstrPIFAddrErrorCause
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* PIF address error during instruction fetch.
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* 15 LoadStorePIFAddrErrorCause
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* Synchronous PIF address error during LoadStore access.
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* 16 InstTLBMissCause
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* Error during Instruction TLB refill
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* 17 InstTLBMultiHitCause
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* Multiple instruction TLB entries matched
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* 18 InstFetchPrivilegeCause
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* An instruction fetch referenced a virtual address at a ring level
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* less than CRING.
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* 19 Reserved for Cadence
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* 20 InstFetchProhibitedCause
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* An instruction fetch referenced a page mapped with an attribute
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* that does not permit instruction fetch.
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* 21..23 Reserved for Cadence
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* 24 LoadStoreTLBMissCause
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* Error during TLB refill for a load or store.
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* 25 LoadStoreTLBMultiHitCause
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* Multiple TLB entries matched for a load or store.
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* 26 LoadStorePrivilegeCause
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* A load or store referenced a virtual address at a ring level less
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* than CRING.
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* 27 Reserved for Cadence
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* 28 LoadProhibitedCause
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* A load referenced a page mapped with an attribute that does not
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* permit loads.
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* 29 StoreProhibitedCause
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* A store referenced a page mapped with an attribute that does not
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* permit stores.
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* 30..31 Reserved for Cadence
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* 32..39 CoprocessornDisabled
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* Coprocessor n instruction when cpn disabled. n varies 0..7 as the
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* cause varies 32..39.
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* 40..63 Reserved
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*
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* Input Parameters:
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* exccause - Identifies the EXCCAUSE of the user exception
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* regs - The register save are at the time of the interrupt.
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*
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* Returned Value:
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* Does not return
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*
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****************************************************************************/
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void xtensa_user_panic(int exccause, uint32_t *regs)
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{
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struct tcb_s **running_task = &g_running_tasks[this_cpu()];
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(*running_task)->xcp.regs = regs;
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up_set_interrupt_context(true);
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/* We get here when a un-dispatch-able, irrecoverable exception occurs */
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board_autoled_on(LED_ASSERTION);
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/* Flush any buffered SYSLOG data (from prior to the error) */
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syslog_flush();
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_alert("User Exception: EXCCAUSE=%04x task: %s\n",
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exccause, get_task_name(running_task()));
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PANIC_WITH_REGS("user panic", regs); /* Should not return */
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for (; ; );
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}
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