zhangyuan29 1dc1e65202 arch/xtensa: use arch atomic when enable iram heap ... S32C1I instructions may target cached, cache-bypass, and data RAM memory locations. S32C1I instructions are not permitted to access memory addresses in data ROM, instruction memory or the address region allocated to the XLMI port. Attempts to direct the S32C1I at these addresses will cause an exception. Signed-off-by: zhangyuan29 <zhangyuan29@xiaomi.com>		2024-12-05 00:05:15 +08:00
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include	arch/xtensa: migrate to SPDX identifier	2024-12-02 17:23:25 +08:00
src	arch/xtensa: use arch atomic when enable iram heap	2024-12-05 00:05:15 +08:00
CMakeLists.txt	cmake:implement CMake build of xtensa arch	2024-11-02 18:08:38 +08:00
Kconfig	arch/toochain: Add toochain to gcc	2024-11-14 15:45:24 +08:00