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c858f3cc44
Implement hardware breakpoint and watchpoint support for TriCore architecture using the Trigger Event (TREVT) registers. This enables the standard NuttX debugpoint API (up_debugpoint_add/remove) on TriCore processors, supporting read/write/execute watchpoints and breakpoints via the on-chip debug unit. Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
148 lines
3.1 KiB
Text
148 lines
3.1 KiB
Text
#
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# For a description of the syntax of this configuration file,
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# see the file kconfig-language.txt in the NuttX tools repository.
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#
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if ARCH_TRICORE
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comment "Tricore Options"
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choice
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prompt "Tricore Toolchain Selection"
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default TRICORE_TOOLCHAIN_GNU
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config TRICORE_TOOLCHAIN_TASKING
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bool "AURIX Tasking C/C++ toolchain"
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select ARCH_TOOLCHAIN_TASKING
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config TRICORE_TOOLCHAIN_GNU
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bool "Generic GNU toolchain"
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select ARCH_TOOLCHAIN_GNU
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---help---
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This option should work for any modern GNU toolchain (GCC 4.5 or newer)
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endchoice # Tricore Toolchain Selection
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config ARCH_TC1V6
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bool
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select ARCH_HAVE_DEBUG
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select ARCH_HAVE_MPU
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select ARCH_HAVE_IRQTRIGGER
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select ARCH_HAVE_PERF_EVENTS
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select ARCH_HAVE_POWEROFF
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select ARCH_HAVE_PERF_EVENTS_USER_ACCESS
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select ARCH_HAVE_SETJMP
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select ARCH_HAVE_RESET
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select ARCH_HAVE_TESTSET
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select ARCH_SETJMP_H
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default n
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config ARCH_TC1V8
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bool
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select ARCH_DCACHE
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select ARCH_HAVE_DEBUG
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select ARCH_ICACHE
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select ARCH_HAVE_MPU
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select ARCH_HAVE_IRQTRIGGER
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select ARCH_HAVE_PERF_EVENTS
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select ARCH_HAVE_PERF_EVENTS_USER_ACCESS
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select ARCH_HAVE_POWEROFF
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select ARCH_HAVE_SETJMP
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select ARCH_HAVE_RESET
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select ARCH_HAVE_TESTSET
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select ARCH_SETJMP_H
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default n
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config ARCH_FAMILY
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string
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default "tc1v6" if ARCH_TC1V6
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default "tc1v8" if ARCH_TC1V8
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config ARCH_CHIP_TC3XX
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bool
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select ARCH_TC1V6
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select ARCH_HAVE_ADDRENV
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select ARCH_HAVE_I2CRESET
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select ARCH_MINIMAL_VECTORTABLE
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select ARCH_MINIMAL_VECTORTABLE_DYNAMIC
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select ALARM_ARCH
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select ONESHOT
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select ONESHOT_COUNT
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---help---
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Infineon aurix tc3xx (six cores)
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config ARCH_CHIP_TC4XX
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bool
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select ARCH_TC1V8
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select ARCH_HAVE_ADDRENV
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select ARCH_HAVE_FPU if !TRICORE_CSRM
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select ARCH_HAVE_I2CRESET
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select ARCH_MINIMAL_VECTORTABLE
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select ARCH_MINIMAL_VECTORTABLE_DYNAMIC
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select ALARM_ARCH
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select ONESHOT
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select ONESHOT_COUNT
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select HAVE_SECURITY_CORE
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---help---
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Infineon aurix tc4xx (six cores and one security core)
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config ARCH_CHIP_TC397
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bool "AURIX CHIP TC397"
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select ARCH_CHIP_TC3XX
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config ARCH_CHIP_TC4DA
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bool "AURIX CHIP TC4DA"
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select ARCH_CHIP_TC4XX
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config ARCH_CHIP
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string
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default "tc397" if ARCH_CHIP_TC397
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default "tc4da" if ARCH_CHIP_TC4DA
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config ARCH_DCACHE_ADDR
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hex "AURIX Dcache base address"
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default 0x7003C000
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---help---
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AURIX Dcache base address, dcache line clear and invalidate need
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use the address.
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config ARCH_MPU_NSETS
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int "Protection sets number"
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default 7
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---help---
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The protection sets count
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config ARCH_MPU_DATA_NREGIONS
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int "Data regions number"
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default 23
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---help---
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The data regions count
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config ARCH_MPU_CODE_NREGIONS
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int "Code regions variables"
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default 15
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---help---
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The code regions count
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config HAVE_SECURITY_CORE
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bool
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---help---
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In addition to the 6 cores, tc4xx also has one more security core.
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config CPU_COREID
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int "TRICORE CPU CORE ID"
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default 0
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range 0 6
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if ARCH_CHIP_TC3XX
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source "arch/tricore/src/tc3xx/Kconfig"
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endif
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if ARCH_CHIP_TC4XX
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source "arch/tricore/src/tc4xx/Kconfig"
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endif
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if ARCH_CHIP_TC397
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source "arch/tricore/src/tc397/Kconfig"
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endif
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if ARCH_CHIP_TC4DA
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source "arch/tricore/src/tc4da/Kconfig"
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endif
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endif # ARCH_TRICORE
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