Commit graph

15824 commits

Author SHA1 Message Date
hujun5
f65a33be8c lc823450_dma: use small lock in arch/arm/src/lc823450/lc823450_dma.c
reason:
We hope to remove all instances of spin_lock_irqsave(NULL).

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-10 01:52:35 +08:00
hujun5
1e64d93a73 s32k3xx_serial: use small lock in arch/arm/src/s32k3xx/s32k3xx_serial.c
reason:
We hope to remove all instances of spin_lock_irqsave(NULL).

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-10 01:29:27 +08:00
hujun5
a68b00206b cxd56_rtc.c: use small lock in arch/arm/src/cxd56xx/cxd56_rtc.c
reason:
We hope to remove all instances of spin_lock_irqsave(NULL).

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-10 01:29:14 +08:00
simbit18
11f412b7af fix nxstyle
Removed extra spaces from .h and .c files
2024-12-10 01:29:00 +08:00
hujun5
1e47441775 max32660_rtc: use small lock in arch/arm/src/max326xx/max32660/max32660_rtc.c
reason:
We hope to remove all instances of spin_lock_irqsave(NULL).

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-09 23:17:22 +08:00
hujun5
0e1b432dd0 armv7/8m: fix regresion from https://github.com/apache/nuttx/pull/14881
reason:
svc call may trigger hardfault

Background
    The origin of this issue is our desire to eliminate the function of storing
"regs" in g_current_regs and instead utilize (*running_task)->xcp.regs for storage.
The benefits of this approach include faster storage speed and
avoiding multiple accesses to g_current_regs during context switching,
thus ensuring that whether returning from an interrupt or an exception,
we consistently use this_task()->xcp.regs

Issue Encountered
    However, when storing registers, we must ensure that (running_task)->xcp.regs is invalid
so that it can be safely overwritten.
According to the existing logic, the only scenario where (running_task)->xcp.regs
is valid is during restore_context. We must accurately identify this scenario.
Initially, we used the condition (running_task)==NULL for this purpose, but we deemed
this approach unsatisfactory as it did not align well with the actual logic.
(running_task) should not be NULL. Consequently, we adopted other arch-specific methods for judgment,
but due to special logic in some arch, the judgment was not accurate, leading to this issue.

Solution:
    For armv6-m, we haven't found a more suitable solution, so we are sticking with (*running_task)==NULL.
    For armv7-m/armv8-m, by removing support for primask, we can achieve accurate judgment.

    PRIMASK is a design in armv6-m, that's why arm introduce BASEPRI from armv7-m.
It's wrong to provide this option for armv7-m/armv8-m arch.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-09 12:20:13 +08:00
hujun5
d20189bdfa armv6m: fix regresion from https://github.com/apache/nuttx/pull/14881
reason:
svc call may trigger hardfalt

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-09 12:20:13 +08:00
Alin Jerpelea
d368c0cc04 arch/arm: migrate to SPDX identifier
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2024-12-06 22:31:35 +08:00
hujun5
1e49cb4828 armv7-a/armv7-r/armv8-r: percpu reg store this_task
This is continue work of https://github.com/apache/nuttx/pull/13726

We can utilize percpu storage to hold information about the
current running task. If we intend to implement this feature, we would
need to define two macros that help us manage this percpu information
effectively.

up_this_task: This macro is designed to read the contents of the percpu
register to retrieve information about the current
running task.This allows us to quickly access
task-specific data without having to disable interrupts,
access global variables and obtain the current cpu index.

up_update_task: This macro is responsible for updating the contents of
the percpu register.It is typically called during
initialization or when a context switch occurs to ensure
that the percpu register reflects the information of the
newly running task.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-06 09:27:33 +08:00
Alin Jerpelea
344968b8c2 arch/arm: migrate to SPDX identifier
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2024-12-06 09:25:23 +08:00
Xiang Xiao
60fb917eda Remove FAR from 32/64bit arch
since these arch doesn't distinguish between near and far pointers

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2024-12-05 22:55:39 +08:00
hujun5
cbd07a86c9 s32k1xx_serial: arch/arm/src/s32k1xx/s32k1xx_serial.c
reason:
We hope to remove all instances of spin_lock_irqsave(NULL).

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-05 22:16:45 +08:00
buxiasen
617fee66ff Revert "arm/rp2040: use custom vectors to make smp_call work with exception_common"
This reverts commit 9464afe7c3.
2024-12-05 20:42:22 +08:00
buxiasen
108aaf8bbb Revert "arm/lc823450: use custom vectors to make smp_call work with exception_common"
This reverts commit c2cb58ff31.
2024-12-05 20:42:22 +08:00
buxiasen
9473cee85b Revert "arm/cxd56: use chip specific vectors to allow smpcall update regs"
This reverts commit 4a1afab88e.
2024-12-05 20:42:22 +08:00
buxiasen
af3c159cff arm-v6/7/8m: sigaction forward to pendsv
For exception directly, tcb->xcp.regs should not be used.

Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2024-12-05 20:42:22 +08:00
buxiasen
55822753be arm-v6/7/8m: sigaction should use running_task
Nested irq possible cause readytorun not match with regs

Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2024-12-05 20:42:22 +08:00
zhangyuan29
1dc1e65202 arch/xtensa: use arch atomic when enable iram heap
S32C1I instructions may target cached, cache-bypass,
and data RAM memory locations. S32C1I instructions
are not permitted to access memory addresses in data ROM,
instruction memory or the address region allocated to
the XLMI port. Attempts to direct the S32C1I at these
addresses will cause an exception.

Signed-off-by: zhangyuan29 <zhangyuan29@xiaomi.com>
2024-12-05 00:05:15 +08:00
zhangyuan29
dcea1b90e7 arch_atomic: only support atomic_xx and atomic64_xx function
Modify the kernel to use only atomic_xx and atomic64_xx interfaces,
avoiding the use of sizeof or typeof to determine the type of
atomic operations, thereby simplifying the kernel's atomic
interface operations.

Signed-off-by: zhangyuan29 <zhangyuan29@xiaomi.com>
2024-12-04 14:03:14 +01:00
Masayuki Ishikawa
6e8375f97b arch: lc823450: Add missing license info to lc823450_symbols.ld
Summary:
- The file includes symbol information provided by ON Semiconductor.
- The license information is the same as lc823450_sdc.c

Impact:
- None

Testing:
- lc823450-xgevk:rndis (build only)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2024-12-04 12:04:38 +01:00
hujun5
79a1ebb9cd rp23xx: use small lock in arch/arm/src/rp23xx/rp23xx_usbdev.c
reason:
We hope to remove all instances of spin_lock_irqsave(NULL).

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-04 14:48:48 +08:00
hujun5
bc844509e2 addrenv: Ensure that the transmission parameter of addrenv_switch is not NULL
reason:
avoid obtaining this_task multiple times.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-04 14:20:12 +08:00
hujun5
d5fba177b1 cxd56xx: use small lock in arch/arm/src/cxd56xx/cxd56_nxaudio_src.c
reason:
We hope to remove all instances of spin_lock_irqsave(NULL).

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-03 23:51:47 +08:00
hujun5
4f3f9751c1 fix compile error
lcd/st7565.c:107:4: warning: #warning "Optimal setting of CONFIG_LCD_MAXCONTRAST is 255" [-Wcpp]
  107 | #  warning "Optimal setting of CONFIG_LCD_MAXCONTRAST is 255"
      |    ^~~~~~~
chip/lc823450_cpuindex.c:36: warning: "CORE_COREID" redefined
   36 | #define CORE_COREID (LC823450_CORE_BASE + 0x0)
      |
In file included from /home/hujun5/downloads1/vela_sim/nuttx/arch/arm/src/common/arm_internal.h:37,
                 from chip/lc823450_cpuindex.c:29:
/home/hujun5/downloads1/vela_sim/nuttx/arch/arm/src/chip/chip.h:48: note: this is the location of the previous definition
   48 | #define CORE_COREID         (LC823450_CORE_BASE + 0)
      |
chip/lc823450_cpuindex.c:37: warning: "CORE_COREID_ID" redefined
   37 | #define   CORE_COREID_ID  (0x1 << 0)
      |
/home/hujun5/downloads1/vela_sim/nuttx/arch/arm/src/chip/chip.h:49: note: this is the location of the previous definition
   49 | #define CORE_COREID_ID      (1 << 0)

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-03 18:27:54 +08:00
hujun5
2b22ee03d6 arm: remove g_running_tasks[this_cpu()] = NULL
reason:
We hope to keep g_running_tasks valid forever.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-03 18:27:54 +08:00
hujun5
03af486d68 arm: remove up_set_current_regs/up_current_regs
reason:
up_set_current_regs initially had two functions:

1: To mark the entry into an interrupt state.
2: To record the context before an interrupt/exception. If we switch to
   a new task, we need to store the upcoming context regs by calling up_set_current_regs(regs).

Currently, we record the context in other ways, so the second function is obsolete.
Therefore, we need to rename up_set_current_regs to better reflect its actual meaning,
which is solely to mark an interrupt.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-03 18:27:54 +08:00
Kyle Wilson
e1e1d534af Add STM32H5 FDCAN Hardware File
Adding the STM32H5 FDCAN Hardware definitions. The register set is identical to the STM32G4. No major changes other than changing G4 to H5 and removing ifdef requirement for STM32G4.

Fixed style issues
2024-12-03 08:33:31 +08:00
Kyle Wilson
d417e1525b First commit of STM32H5 SPI Hardware file.
This file is heavily based on the STM32H7 implementation. CFG1_BPASS and UDRCFG were the main differences.
2024-12-03 08:32:50 +08:00
Michal Lenc
9fbb81e8a4 samv7: fix bytes to words calculation in user signature read
EEFC read sequence requires read length in words instead of bytes,
therefore bytes given by the user has to be recalculated to words.
The calculation however had a mistake in brackets and was just adding
1 to buflen instead of recalculating it to 4 byte words. This caused
global array g_page_buffer to overflow for some reads.

This fixes the calculation.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2024-12-02 19:47:43 +08:00
hujun5
8b46a4d916 lc823450_usbdev: use small lock in arch/arm/src/lc823450/lc823450_usbdev.c
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-02 13:35:14 +08:00
hujun5
c116b6578a max32660_wdt: use small lock in arch/arm/src/max326xx/max32660/max32660_wdt.c
reason:
we plan to remove all instances of spin_lock_irqsave(NULL)

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-02 13:34:53 +08:00
hujun5
30940d9251 imxrt_serial: use small lock in arch/arm/src/imxrt/imxrt_serial.c
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-01 18:02:10 +08:00
wangjianyu3
074c494f8f nrf91: Support using different nbuffer for each topic
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
2024-11-30 14:10:57 +08:00
hujun5
74dfcdfbd6 cxd56xx: use small lock in arch/arm/src/cxd56xx/cxd56_clock.c
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-11-30 03:15:02 +08:00
chao an
8257b11944 arm/isr: move up_set_interrupt_context() to chip define
up_set_interrupt_context() is chip specific implement, move this function to correct place

Signed-off-by: chao an <anchao@lixiang.com>
2024-11-29 18:37:08 +08:00
simbit18
9c9b945876 fix nxstyle
Removed extra spaces from .h and .c files
2024-11-28 20:40:13 +08:00
hujun5
0bba53ce12 remove redundant scheduling records
reason:
Since the scheduling records have already been moved to the interrupt exit in this submission,
we need to delete the original records' locations.
This commit fixes the regression from https://github.com/apache/nuttx/pull/13651

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-11-28 18:56:13 +08:00
simbit18
0476895c0d fix nxstyle
Remove TABs
2024-11-28 09:14:49 +08:00
Jinliang Li
37a0445ddb armv8-r/gicv3: support fiq
1. support fiq decoding and dispatch
2. replace CONFIG_ARMV8R_DECODEFIQ with CONFIG_ARCH_HIPRI_INTERRUPT

Signed-off-by: Jinliang Li <lijinliang1@lixiang.com>
2024-11-27 14:28:27 +08:00
hujun5
ef313755e7 sched: replace up_cpu_index with this_cpu
Make this_cpu is arch independent and up_cpu_index do that.
In AMP mode, up_cpu_index() may return the index of the physical core.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-11-27 03:00:32 +08:00
hujun5
610efc8f1a arm: remove up_set_current_regs/up_current_regs
reason:
up_set_current_regs initially had two functions:

1: To mark the entry into an interrupt state.
2: To record the context before an interrupt/exception. If we switch to
   a new task, we need to store the upcoming context regs by calling up_set_current_regs(regs).

Currently, we record the context in other ways, so the second function is obsolete.
Therefore, we need to rename up_set_current_regs to better reflect its actual meaning,
which is solely to mark an interrupt.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-11-26 20:04:54 +08:00
hujun5
03f430edf7 fix some build error
hujun5@hujun5-OptiPlex-7070:~/downloads1/vela_sim/nuttx$ make -j12
chip/qemu_boot.c: In function 'up_cpu_start':
chip/qemu_boot.c:102:3: warning: implicit declaration of function 'sched_note_cpu_start' [-Wimplicit-function-declaration]
  102 |   sched_note_cpu_start(this_task(), cpu);
      |   ^~~~~~~~~~~~~~~~~~~~
chip/qemu_boot.c:102:24: warning: implicit declaration of function 'this_task' [-Wimplicit-function-declaration]
  102 |   sched_note_cpu_start(this_task(), cpu);
      |                        ^~~~~~~~~

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-11-25 17:10:50 +08:00
yinshengkai
0194c2f88a gcov: update gcov compilation parameters
profile-generate is used to generate compilation feedback optimization data, not just code coverage data

It will rely on the toolchain library:
nuttx/libs/libc/misc/lib_utsname.c:94:(.text.uname+0x2c): undefined reference to `__gcov_indirect_call_profiler_v4'
arm-none-eabi-ld: nuttx/libs/libc/misc/lib_utsname.c:113:(.text.uname+0x178): undefined reference to `__gcov_indirect_call'
arm-none-eabi-ld: nuttx/libs/libc/misc/lib_utsname.c:113:(.text.uname+0x188): undefined reference to `__gcov_time_profiler_counter'
arm-none-eabi-ld: nuttx/staging/libc.a(lib_utsname.o):(.data..LPBX0+0x30): undefined reference to `__gcov_merge_time_profile'

Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2024-11-22 19:08:08 +08:00
simbit18
d16de91e39 [MSYS2] CMake+Ninja Fix arm-none-eabi-ar: Argument list too long
This issue is related to the Arm toolchain for Windows which is available for x86 host architecture only (compatible with x86_64)

Windows (mingw-w64-i686) hosted cross toolchains
AArch32 bare-metal target (arm-none-eabi)

Issue
/bin/sh: line 1: /home/nuttx/nuttxnew/tools/gcc-arm-none-eabi/bin/arm-none-eabi-ar: Argument list too long

On Windows, arm-none-eabi-ar can only accept strings up to a maximum length of 32,768 characters.

We could suppress the 32K include string limitation by setting the CMake variable CMAKE_NINJA_FORCE_RESPONSE_FILE to ON.

This is unfortunately not enough!!! ): In the build phase this error comes out

$ cmake --build build
[2/1025] Building ASM object arch/CMakeFiles/arch.dir/arm/src/armv7-m/arm_exception.S.obj
FAILED: arch/CMakeFiles/arch.dir/arm/src/armv7-m/arm_exception.S.obj
/home/nuttx/nuttxnew/tools/gcc-arm-none-eabi/bin/arm-none-eabi-gcc.exe @arch/CMakeFiles/arch.dir/arm/src/armv7-m/arm_exception.S.obj.rsp -MD -MT arch/CMakeFiles/arch.dir/arm/src/armv7-m/arm_exception.S.obj -MF arch/CMakeFiles/arch.dir/arm/src/armv7-m/arm_exception.S.obj.d -o arch/CMakeFiles/arch.dir/arm/src/armv7-m/arm_exception.S.obj -c /home/nuttx/nxninja/nuttx/arch/arm/src/armv7-m/arm_exception.S
C:/msys64/home/nuttx/nxninja/nuttx/arch/arm/src/armv7-m/arm_exception.S:42:10: fatal error: nuttx/config.h: No such file or directory
   42 | #include <nuttx/config.h>
      |          ^~~~~~~~~~~~~~~~
compilation terminated.

The Workround I found to solve this problem is to overwrite
the responsible file flag CMAKE_${lang}_RESPONSE_FILE_FLAG with $DEFINES $INCLUDES $FLAGS

Maybe there is a better solution but this one it works. :)
2024-11-21 19:18:38 -03:00
guoshichao
f6cfcfa39f armv6-m: fix the incorrect stub-function entry address of svc call
the stub-function entry address is stored in r4, we should branch to the
stub-function with blx r4, not r5

Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2024-11-21 20:08:42 +08:00
Peter Bee
3e6913775d fix(rp2350): should copy data before init clock
Signed-off-by: Peter Bee <peter@PeterdeMac-mini.local>
2024-11-21 20:00:17 +08:00
stbenn
9cd0ea32ea arch/stm32h5: Add timer register hardware file
This commit adds register definitions for advanced, basic, and general purpose timers. Formatting convention was taken from the H7 hardware timer header.
2024-11-21 10:54:10 +08:00
simbit18
7df0e945ad Fix Kconfig style
Remove spaces from Kconfig files
Add TABs
Replace help => ---help---
Remove extra TABs
Add comments
2024-11-20 16:45:40 -03:00
Peter Bee
c0f776dbc3 follow upstream change & fix minor things
Signed-off-by: Peter Bee <pbjd97@gmail.com>
2024-11-20 16:32:05 -03:00
Peter Bee
48ded21e30 refine driver
Signed-off-by: Peter Bee <pbjd97@gmail.com>
2024-11-20 16:32:05 -03:00