Rename IMX9_IRQ_uSDHC{1,2,3} to IMX9_IRQ_USDHC{1,2,3} in both arm
and arm64 imx95_irq.h to follow the all-caps naming convention used
by imx93_irq.h and the rest of the NuttX codebase. Remove the now
unnecessary USDHC IRQ alias block from arm64 imx95_irq.h.
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
* Fix GPIO unspecified behavior on some GPIO ports.
* Fix GPIO undefined behavior caused by uncleared set or reset bits.
Signed-off-by: Saurav Pal <resyfer.dev@gmail.com>
<nuttx/irq.h> will use the macros defined in <arch/chip/irq.h>, so the include order should be after it
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
Add CONFIG_BUILD_PROTECTED support alongside
CONFIG_BUILD_KERNEL for saved register
pointers and task startup functions. Fix
arm64_fork() to properly handle Thumb bit masking.
Enable weak_function for up_allocate_kheap()
to support board-specific heap allocation.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Rename arm64_addrenv.c to arm64_addrenv_mmu.c to separate MMU-specific logic.
Add new arm64_addrenv_mpu.c with stub implementations of address environment
functions for MPU-based systems. Enable address environment support in FVP ARMv8-R
Kconfig to support kernel stacks in protected mode. Conditionally build MPU or
MMU address environment code based on CONFIG_ARCH_USE_MMU/CONFIG_ARCH_USE_MPU.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Rename STACK_ALIGNMENT macro to STACKFRAME_ALIGN throughout the codebase
to provide clearer naming semantics. The new name better reflects the macro's
purpose of frame alignment rather than general stack alignment.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Add support to disable signals actions related struct
Co-authored-by: guoshichao <guoshichao@xiaomi.com>
Signed-off-by: Chengdong Wang <wangchengdong@lixiang.com>
1. up_irq_save should not mask fiq if CONFIG_ARCH_HIPRI_INTERRUPT=y
2. up_irq_save should mask fiq if CONFIG_ARCH_TRUSTZONE_SECURE=y
3. up_irq_save should mask irq if CONFIG_ARCH_TRUSTZONE_SECURE=n
4. add up_secure_irq in arm64
5. add ARCH_HAVE_TRUSTZONE support for ARCH_CORTEX_R82
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Gdbstub demo::
The Qemu version must be above 9.2 to support two serial ports.
One window:
./tools/configure.sh qemu-armv8a:gdbstub; make -j25
qemu-system-aarch64 -cpu cortex-a53 -nographic -machine virt,virtualization=on,gic-version=3 -net none -kernel ./nuttx -serial mon:stdio -serial pty
char device redirected to /dev/pts/27 (label serial1)
- Ready to Boot Primary CPU
- Boot from EL2
- Boot from EL1
- Boot to C runtime for OS Initialize
Another window:
gdb-multiarch nuttx -ex "target remot /dev/pts/27"
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License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.
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Type "show configuration" for configuration details.
For bug reporting instructions, please see:
<https://www.gnu.org/software/gdb/bugs/>.
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Reading symbols from nuttx...
Remote debugging using /dev/pts/26
gdb_get_registers (state=0x403e1590) at gdbstub/lib_gdbstub.c:1020
1020 reg = state->running_regs;
(gdb) c
Signed-off-by: hujun5 <hujun5@xiaomi.com>
error: unpredictable STXR instruction, status is also a source
99 | "stxr %w0, %1, [%2] \n"
| ^
<inline asm>:5:10: note: instantiated into assembly here
5 | stxr w10, x10, [x9]
Using w0 to pass the result can cause the "status register is also a source" problem, resulting in unpredictable behavior.
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
common/arm64_cache.c:305:38: error: value size does not match register size specified by the constraint and modifier [-Werror,-Wasm-operand-widths]
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
This implements an interrupt-based SPI driver for the BCM2711 SPI
interfaces (excluding auxiliary SPI interfaces). Only tested on SPI0
since proprietary firmware does not initialize any other SPI interfaces,
and doing so will require reverse engineering.
This adds support for the i.MX9 ROMAPI, allowing boot in a more
device agnostic and portable manner. The ROMAPI "natively" allows to:
- Query the boot device for information.
- Copy data from the boot device to RAM.
An extra functionality was added to ROMAPI to calculate
offsets of sequential AHAB containers.
The AHAB functionality is built on top of raw ELE primitives and allows to:
- Authenticate a container image.
- Release the authenticated container.
Signed-off-by: Theodore Karatapanis <tkaratapanis@census-labs.com>
So far NuttX has supported OP-TEE interfacing over
local and RPMsg sockets. This commit introduces support
for direct invocation of OP-TEE through arm SMCs. The
SMC transport is enabled through CONFIG_DEV_OPTEE_SMC.
This SMC implementation has been tested only with arm64,
OP-TEE rev 4.4.
Note that it does not support reverse direction RPCs,
i.e. from the Secure World to the Normal World to
something like optee supplicant. A basic RPC handling
skeleton is provided with implementation for some
basic functions (alloc/free mem, and foreign interrupts)
but no supplicant command handling.
(+one minor change s/parm/param in arch/arm64/include/syscall
to satisfy the spellchecker during PR)
Signed-off-by: George Poulios <gpoulios@census-labs.com>
This PR adds support for the Allwinner A527 Arm64 SoC.
This will be used by the upcoming port of NuttX for
PINE64 Yuzuki Avaota-A1 SBC.
Most of the code was derived from NuttX for
QEMU Arm64 Kernel Build qemu-armv8a:knsh.
The modified code is explained here:
https://lupyuen.github.io/articles/avaota#appendix-port-nuttx-to-avaota-a1
Modified Files in arch/arm64:
Kconfig: Added ARCH_CHIP_SUNXI for Allwinner 64-bit SoCs.
Added ARCH_CHIP_SUNXI_A527 for A527 SoC.
New Files in arch/arm64:
include/a527/chip.h: A527 Definitions
include/a527/irq.h: External Interrupts
src/a527/chip.h: Memory Map
src/a527/a527_boot.c, a527_boot.h: Startup Code
src/a527/a527_initialize.c: Power Management
src/a527/a527_lowputc.S: UART Output
src/a527/a527_serial.c: Serial Driver
src/a527/a527_textheap.c: Text Heap
src/a527/a527_timer.c: A527 Timer
src/a527/Kconfig: A527 Config
src/a527/Make.defs, CMakeLists.txt: Makefiles
Signed-off-by: Lup Yuen Lee <luppy@appkaki.com>
Make sure the registers context size is aligned to 16bytes as required by armv8-a.
This issue has been reported earlier, thus make sense to make sure it won't happen in future.
Signed-off-by: Neo Xu <neo.xu1990@gmail.com>
zynq-mpsoc and zcu111 borad was broken by #15437, because #15437 changes
ARM64_CONTEXT_REGS from 36 to 37, resulting in the stack no longer being
16-byte aligned which appears to violate the ARMv8-A architecture's
requirement for 16-byte stack alignment. this commit changes ARM64_CONTEXT_REGS
to 38 to fix this issues.
The method is the same as the method of saving the current DAIF state of the thread
It will pave the way for the future implementation of hwasan's memory management
Allows each thread to independently control the mte switch function
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
Inline & inline_function both used make confuze, let's modify all inline
in irq.h to inline_function, also clear the always_inline_funcion
declaration.
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
Includes a Mini-UART NSH console for the 4B, tested on the 4GB RAM
model. Part of an I2C driver which can only read, boiler-plate for a SPI
driver, and a GPIO driver with limited pins. Some tools are present for
automatically fetching the boot files and creating the `config.txt` file
based on selected Kconfig options.
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
reason:
up_set_current_regs initially had two functions:
1: To mark the entry into an interrupt state.
2: To record the context before an interrupt/exception. If we switch to
a new task, we need to store the upcoming context regs by calling up_set_current_regs(regs).
Currently, we record the context in other ways, so the second function is obsolete. Therefore,
we need to rename up_set_current_regs to better reflect its actual meaning, which is solely to mark an interrupt.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
time/lib_localtime.c: In function 'tz_lock':
time/lib_localtime.c:396:7: error: 'tpidr_el1' undeclared (first use in this function)
396 | if (up_interrupt_context() || (sched_idletask() && OSINIT_IDLELOOP()))
| ^~~~~~~~~~~~~~~~~~~~
Signed-off-by: ligd <liguiding1@xiaomi.com>
when we build mbedtls in vela with ghs compiler, the mbedtls need to
access __ARM_ARCH and __ARM_FEATURE_DSP, and to construct the inline asm
code based on these two macros.
With ghs compiler, these two macros are not defined, and will be
evaluated as 0 by default, and thus will using to wrong inline asm code,
in order to handle this issue, we need to add conversion between the ghs
and gcc with __ARM_ARCH, __ARM_FEATURE_DSP
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
If the core id needs to be included in the hardware register
calculation, up_cpu_index() should be used instead of this_cpu().
Signed-off-by: chao an <anchao@lixiang.com>
Some app with same code runs on different cores in AMP mode,
need the physical core on which the function is called.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
Since FPU is now always saved into the current process stack location
upon exception entry, there is no need to keep fpu_regs (or saved_fpu_regs)
in the TCB.
