Commit graph

18069 commits

Author SHA1 Message Date
xiaoxiang
0371a4df22 Revert "sim: add popen and pclose to nuttx-name.in"
This reverts commit 6eb29f9715.

Reason for revert: don't need

Change-Id: If600953ae9b2de006e1ce319c68343f1c21facf9
2021-08-20 22:06:37 +08:00
Jiuzhu Dong
6eb29f9715 sim: add popen and pclose to nuttx-name.in
Change-Id: Id439ce5e308ce3ae0b618b4752e57965aa98f669
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
2021-08-19 22:53:13 +08:00
chao.an
59e2e5fdc8 arch/arm: correct the frame pointer register declare
In AArch32, the frame pointer is stored in register R11 for ARM code or register R7 for Thumb code.
In AArch64, the frame pointer is stored in register X29.

Change-Id: I0c60cf37bea9bb94b9c2043b4c97e06001214a54
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-08-18 19:37:01 +08:00
chao.an
0eba5015dd riscv/common: add CURRENT_REGS declare in RV32
Change-Id: I92322a707b29bf1389ba81da118fb8be61877531
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-08-18 19:36:09 +08:00
jordi
cd2fbf0b3c Kconfig: add quotes in source to clean warnings from setconfig
To avoid the setconfig warning "style: quotes recommended around xxx in
source xxx"

Change-Id: Iaec3ae59ba2ec15337652c9962b25081ff03e1d7
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-08-18 19:35:59 +08:00
Xiang Xiao
e91c95b197 mtd: Implement BIOC_PARTINFO for all drivers
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-08-16 22:07:02 +08:00
Xiang Xiao
93b478a71f arch/arm: Add NVIC_FPCCR_XXX macro to avoid the hard code value
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-08-15 10:18:19 -07:00
Xiang Xiao
642443b8b3 arch/arm: Add NVIC_CPACR_CP_XXX(n) macro to avoid the hard code value
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-08-15 10:18:06 -07:00
Xiang Xiao
8c38d134f8 arch/arm: Add NVIC_AIRCR_VECTKEY macro to avoid the hard code value
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-08-15 10:17:54 -07:00
zhuyanlin
9d92277bb8 arch:xtensa: replace include file from src/chip_xxx to chip.h
Use chip.h as a standard include file, replace chip_xxx in src dir
2021-08-13 13:56:39 +08:00
zhuyanlin
7b1d3d5c75 arch:esp: create chip.h header for chip src code.
Create chip.h header for esp src code.
2021-08-13 13:56:35 +08:00
zhuyanlin
43b72c180a arch:xtensa: add __ASSEMBLY__ for espxxx_soc.h
Those header contain syntax not be recognize by gnu assembler.
2021-08-13 13:56:31 +08:00
Xiang Xiao
4bee1e5690 mtd: Replace MTDIOC_XIPBASE with BIOC_XIPBASE
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-08-12 20:29:18 +08:00
Xiang Xiao
9b58b77b88 mtd: Remove the empty MTDIOC_XIPBASE implmentation
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-08-11 23:39:24 +08:00
Gustavo Henrique Nihei
845b1e8043 risc-v/esp32c3: Implement MTDIOC_ERASESTATE for SPI Flash driver
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-08-11 23:37:48 +08:00
Gustavo Henrique Nihei
66aa221947 arm/lpc43xx: Implement MTDIOC_ERASESTATE for SPIFI Flash driver
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-08-11 23:37:48 +08:00
Gustavo Henrique Nihei
5784d1384b xtensa/esp32: Implement MTDIOC_ERASESTATE for SPI Flash driver
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-08-11 23:37:48 +08:00
zhuyanlin
62ce5ca966 xtensa:coproc: fix XTENSA_CP_ALLSET error in some case
Consider follow coprocessor configuration case:

\#define XCHAL_CP_NUM                    1       /* number of coprocessors */
\#define XCHAL_CP_MAX                    2       /* max CP ID + 1 (0 if none) */
\#define XCHAL_CP_MASK                   0x02    /* bitmask of all CPs by ID */
\#define XCHAL_CP_PORT_MASK              0x00    /* bitmask of only port CPs */
\
\#define XCHAL_CP1_NAME                  "AudioEngineLX"
\#define XCHAL_CP1_IDENT                 AudioEngineLX
\#define XCHAL_CP1_SA_SIZE               208     /* size of state save area */
\#define XCHAL_CP1_SA_ALIGN              8       /* min alignment of save area */
\#define XCHAL_CP_ID_AUDIOENGINELX       1       /* coprocessor ID (0..7) */

In this case, XTENSA_CP_ALLSET is 0x1, but valid coprocessors
bitmap is 0x2, use marco XCHAL_CP_MASK instead, it is bitmap of all
vaild coprocs.

Change-Id: I63ec01e4bd0cbafc62d56636cc11bdc4a2f7857f
2021-08-11 10:40:01 +08:00
zhuyanlin
dd2f465055 arch:xtensa: add arch stdarg.h include file for xtensa
Add arch/include/stdarg.h for xtensa.

Change-Id: Ia914ca0f4c95e86b130983ce690479a994a08b56
2021-08-11 10:39:44 +08:00
Xiang Xiao
d27a86486f fs/hostfs: Support fchstat and chstat callback
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-08-10 14:33:14 +08:00
Xiang Xiao
e09dc6069b arch/arm: Add CONTROL register bit field definition
and replace all hardcode value

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-08-09 21:08:29 +08:00
zhuyanlin
cca615e35f arch:xtensa:include chip/irq.h instead of depend on chip config.
Many duplicate code when more chips add-in,
follow arch/arm/include/irq.h method, use chip/irq.h instead.

Change-Id: I42f516c1dda68e973939c669f627c457cd0bc65e
2021-08-05 14:07:08 +08:00
zhuyanlin
2152ec3fbb arch:xtensa_testset: remove include arch/spinlock.h
In config with no "CONFIG_SPINLOCK", include arch/spinlock.h will lead to
build error as multi definition with spinlock_t. Nuttx/spinlock.h will
include arch/spinlock.h when needed.

Change-Id: I33b48503f679ec79af3a0ef1f0fb1536aaf1ce7c
2021-08-05 14:07:08 +08:00
zhuyanlin
acf8d58472 arch:xtensa: use letter 'i' in inline assemble constraint instead of I
Some toolchain such as xtensa-xcc is unrecognize with constraint letter 'I',
letter 'i' is more common in GNU assembler.

Change-Id: I00f6a33fd7a5f2b95508c683e9954d402b68755f
2021-08-05 14:07:08 +08:00
zhuyanlin
15abaf6eaa arch:xtensa: add multi GNU toolchain for xtensa.
Add support xcc/xclang/esp GUN toolchin in xtensa,
ESP toolchain is default.

Change-Id: Id00bcf4a16c1e16862a106db32b1da3f3713a14c
2021-08-05 14:07:08 +08:00
liuhaitao
694e7d29f4 armv8-m: correct CONFIG_SYS_RESERVED from 8 to 9 accordingly
Signed-off-by: liuhaitao <liuhaitao@xiaomi.com>
Change-Id: I94a24140c57f21e80b7a0c517e7458adf23e2c88
2021-08-04 22:42:50 +08:00
Xiang Xiao
030d496728 Fix the printf warning after off_t change
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Id46daa2ee690a73d3187b479f0e7ab0e2e361764
2021-08-04 16:13:25 +08:00
licheng
aad8396354 EXC_SECURE and SECURE_STACK just can clear at TRUSTZONE_NONSECURE 2021-08-04 10:39:35 +08:00
liuhaitao
d54b066e8f Revert "Revert "armv8-m: Fix EXC_RETURN for non-secure usage""
This reverts commit 48beda08e2.

Signed-off-by: liuhaitao <liuhaitao@xiaomi.com>
Change-Id: I5094d94ee64182b346fbcf6d7695b6259e3b006a
2021-08-04 10:39:35 +08:00
liuhaitao
a0de639ca3 Add the missing SYS_pthread_exit in armv8-m svcall.h
Signed-off-by: liuhaitao <liuhaitao@xiaomi.com>
Change-Id: I42acaab45420aa123221b8832996b23ff412f575
2021-08-03 22:08:26 +08:00
ligd
b09c2b42dd arm: add ARM_HAVE_NEON to Kconfig
Change-Id: I112037aa15a6fae76cf4b7c2df10a42899c38a61
Signed-off-by: ligd <liguiding1@xiaomi.com>
2021-07-30 14:31:39 +08:00
丁欣童
92be27f157 Use exit func iml host_abort.
N/A

When use poweroff command,host_abort will be called,but may be make __stack_chk_fail irq, and host_abort be called in PANIC(), so bring infinite loop, in turn it can not exit SIM.

Signed-off-by: 丁欣童 <dingxintong@xiaomi.com>
Change-Id: If428e5fc65ace053420cc85c809ed7010b3df7d1
2021-07-30 11:46:33 +08:00
Jiuzhu Dong
20ff96a58d Revert "sim: change ownership to user ID of the calling process for shm file"
This reverts commit 03c1496e8e.
2021-07-29 23:01:08 +08:00
liucheng5
d82a248863 feature: driver: Add a Linux SPI into simulator.
N/A

When SIM_SPI is valid, a specified Linux SPI device ‘spidevN.P’(N is bus number and P is CS number) is attached to nuttx simulator, shown as 'spi0' under /dev. One may type spi command (need SPITOOL valid) in NSH to control the Linux SPI and exchange data, other devices such sensors can use it to debug in simulator on a Ubuntu PC. Note that a USB<>SPI module (e.g. CH341A/B) should be plugged in to achieve Linux SPI ports.

Change-Id: I275b2c2bbf6d14bcdf514c89efb9a2264d69e9a3
Signed-off-by: liucheng5 <liucheng5@xiaomi.com>
2021-07-28 10:05:26 +08:00
zhuyanlin
b0dbde28a5 arch:xtensa:vector: fix typo error in level4_ventor
Change-Id: I66cd3ff30e50e18ed718499aef609dd7aeb82dd3
2021-07-27 16:26:55 +08:00
zhuyanlin
39e702ab5d arch: xtensa: save current SP before overwrting in dispatch_c_isr.
In levelx(2,3,4,5)_handler, first need to save sp in a12,
then after dispatch_c_isr we can restore sp from a12.

Change-Id: Idb6b64a782da866670a4db80b33435a9b63f02c3
2021-07-27 16:26:50 +08:00
Xiang Xiao
ba9396d827 arch/sim: Copy include/nuttx/config.h to the local folder
so the source code compiled by host environment can include config.h
directly and then avoid pass Kconfig option through Makefile manually

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Ic9fe6f846082cef2d0808dc717df8ae6ed929edf
2021-07-27 11:08:58 +08:00
Xiang Xiao
ccb8538b6d sim: Correct the typedef in nuttx/hostfs.h
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I5fbfd519417c5686325822549c068b1d42f83946
2021-07-27 11:08:47 +08:00
Jiuzhu Dong
03c1496e8e sim: change ownership to user ID of the calling process for shm file
Change-Id: Ia0b5721421c2eb7fb408d55a26f821d6e95202df
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
2021-07-23 21:55:15 +08:00
ligd
5988732436 arm: add up_secure_irq support
Change-Id: Ibc9402dcef4045ca122da400940d57de6b508308
Signed-off-by: ligd <liguiding1@xiaomi.com>
2021-07-22 12:02:06 +08:00
ligd
c4b1720b98 arch: add depends to trigger_irq
Change-Id: I334f625f8f1a6ebaa4fa5ea292de142a93120f51
Signed-off-by: ligd <liguiding1@xiaomi.com>
2021-07-22 12:02:06 +08:00
Jiuzhu Dong
8b4749f89f sim/rptun: optimize multi-core startup
Don't need to wait each other.

Change-Id: I6172823c84a96e4082fa5f33bdb05d7bd1d3b056
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
2021-07-20 18:27:11 +08:00
Xiang Xiao
a27f0defa8 sim/rptun: Trigger the callback only the sequnece number change
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I4fc8b876541ccb6ee12fa92145628eece0b90e3c
2021-07-20 17:59:53 +08:00
ligd
36ecaa87d1 ARM: fix CPSR corruption after exception handling
It seems to be caused by the corrupted or wrong CPSR restored on return
from exception. NuttX restores the context using code like this:

    msr spsr, r1

GCC translates this to:

    msr spsr_fc, r1

As a result, not all SPSR fields are updated on exception return. This
should be:

    msr spsr_fsxc, r1

This bug has been fixed by Heesub Shin in:
343243c7c0

Change-Id: Ibc64db7bceecd0fb6ef39284fb5bc467f5603e2e
2021-07-19 20:48:00 +08:00
Jiuzhu Dong
bd1a7259fa sim/cmdline: save boot cmdline
Change-Id: I989850a09528e3868957284c9f419d0992ae8d1f
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
2021-07-17 14:02:07 +08:00
Xiang Xiao
e6d9be25b4 arch/sim: The second CPU shouldn't call up_irqinitialize
since the signal handler the process concept

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-07-17 13:34:06 +08:00
Xiang Xiao
5589ad406a arch: Fix rtcb can't found error
use the same condition check in declaration and reference

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I7b05316e914708fceeddac394d784ee3720a3c1b
2021-07-17 13:33:20 +08:00
Xiang Xiao
e194867de4 arch/sim: Remove the unused sim_host_timer_handler
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Icacbe74308580b7fc2449cdf9e41f85fce43d5a4
2021-07-16 23:17:10 +08:00
Xiang Xiao
5d9a22a0bb arch/sim: Initialize the idle thread stack info correctly
and change the default value of IDLETHREAD_STACKSIZE to 65536

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Ia54efbbca4b69706150bc4178844b316688a104e
2021-07-16 11:19:56 +08:00
Virus.V
2859f5e972 risc-v/bl602: update wifi firmware and some fixup.
1. Added check for repeated connection wifi operations.
2. Invoke the carrier on/off operation in the wrong place.
3. The RTC initialization time is incorrect.
4. Reserve 32K I-Cache space in the linker script.
5. Increase the size of the wifi firmware receiving buffer.

Signed-off-by: Virus.V <virusv@live.com>
2021-07-14 19:51:01 +08:00