1. Changes the phyadd to 0xC to speed up the training of phyadd.
2. Set RX DMA buffer size configureable.
3. Create netnsh configs as ethernet boot from QSPI FLASH.
4. Fix some typo in #15720 which is nonsynchronous with local code.
PIC(Position-Independent-Code) board could work on cmake:
cmake -B ap -DBOARD_CONFIG=mps3-an547:ap -GNinja
Signed-off-by: chao an <anchao.archer@bytedance.com>
Make sure the registers context size is aligned to 16bytes as required by armv8-a.
This issue has been reported earlier, thus make sense to make sure it won't happen in future.
Signed-off-by: Neo Xu <neo.xu1990@gmail.com>
zynq-mpsoc and zcu111 borad was broken by #15437, because #15437 changes
ARM64_CONTEXT_REGS from 36 to 37, resulting in the stack no longer being
16-byte aligned which appears to violate the ARMv8-A architecture's
requirement for 16-byte stack alignment. this commit changes ARM64_CONTEXT_REGS
to 38 to fix this issues.
Zynq MPSOC The processing system (PS) is equipped with four gigabit
Ethernet controllers.Each controller can be configured independently.
Each controller uses a reduced gigabit media independent interface (RGMII)
v2.0. This commit add support for ethernet of ZYNQ MPSOC.
Summary:
- Added `--print-memory-usage` to `LDFLAGS` in `Toolchain.defs` for both `lx6` and `lx7` architectures
- This flag enables memory usage reporting during the linking phase, providing better visibility into memory allocation
Impact:
- No functional changes - the flag only adds additional debug information during the build process
- Improves debugging and optimization capabilities by providing detailed memory usage statistics
- Maintains compatibility with existing build configurations and toolchains
Testing:
Test result on esp32s3:
```
Memory region Used Size Region Size %age Used
ROM: 556116 B 16777184 B 3.31%
iram0_0_seg: 23296 B 304 KB 7.48%
irom0_0_seg: 621652 B 16777184 B 3.71%
dram0_0_seg: 85780 B 288 KB 29.09%
drom0_0_seg: 157180 B 16777184 B 0.94%
rtc_iram_seg: 0 B 8168 B 0.00%
rtc_data_seg: 0 B 8168 B 0.00%
rtc_reserved_seg: 0 B 24 B 0.00%
rtc_slow_seg: 0 B 8 KB 0.00%
```
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
What's really need is a done signal sent from the secondary
cpu to the boot cpu, so let's simplify the logic by:
1.Change the spinlock to a bool flag
2.Set the flag to true in the secondary cpu
3.Wait the flag set in the boot cpu before continue booting
This also remove all bad usage of spinlock from the code base:
1.Lock spinlock in one thread, but unlock in a different thread
2.Lock spinlock twice in one thread, but unlock only once
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Also errors which currently return other than -EAGAIN, are typically
recoverable with retraining. So just re-try trainining 20 times on any
error, resetting the controller in between.
Only reset if it is not recovered in this time.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
So far only USART drivers could use TX/RX DMA. This commit adds the
support for UART drivers as well (with the exception of serial console).
UART peripheral does not have timeout interrupt, so external polling
is required to flush the RX data from DMA buffers even if the buffer
is not yet full. The board layer can do this by calling
sam_serial_dma_poll function.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
If scratchpad is being used, the cache way 0, which is automatically
enabled at boot, needs to be re-configured as part of scratchpad memory
Otherwise there is a possibility of random memory corruption in the
scratchpad
area due to cache eviction from way 0.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Summary:
- Unified the specification of LLVM architecture and ABI types across the CMake and Makefile configurations.
- Introduced `LLVM_ARCHTYPE` and `LLVM_CPUTYPE` variables in the CMake configuration to match the Makefile's approach.
- Standardized the ABI type (`LLVM_ABITYPE`) to `sysv` for both Linux and macOS host configurations.
Impact:
- Ensures consistent LLVM target definitions across build systems (CMake and Makefile).
- Simplifies future maintenance by avoiding divergence in LLVM-related configurations.
- No functional changes to the build output; only the internal representation of LLVM target information is aligned.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Progress in USB driver
Nothing is working yet. But just getting this in here so it is saved.
Minor changes with USB power enabled
Serial over USB is working now.
Removed stm32_usbdev.c, added stm32_usbfs.c. Still needs review before pull-request.
Rewrote VDDUSB valid check to use register definitions. Wait for USB33RDY before moving on. Also style updates.
Renamed stm32_usbdev files to stm32_usbfs. Renamed STM32H5 configuration options from STM32H5_USB to STM32H5_USBFS. Properly named REGDEBUG defines. Added STM32H5_USB_REGDEBUG to Kconfig and updated stm32_usbfs.c to use it. TRACE functionality still needs work.
Updated REGDEBUG for 32-bit register accesses.
More style updates.
Added usbnsh defconfig to nucleo-h563zi
Update to allow 16 buffers (max for 8 endpoints). Renamed lpinterrupt and lptransfer. Changed board.h to use SYNCSRC_USB only if USB is enabled.
Buffer size is still set to max packet size of 64 bytes, because we are using a full-speed peripheral. It is unclear to me whether having a buffer larger than the max packet size has any benefit. Double buffering is a way to increase throughput, though that still needs to be implemented.
Adapted USBFS Buffer table for 32-bit accesses.
Style updates
Build stm32_hsi48.c based on CONFIG_STM32H5_HAVE_HSI48.
Change LPMODE CNTR bit to SUSPRDY.
fix smp crash on sabre-6quad/smp, regression from:
|commit 1e49cb4828
|Author: hujun5 <hujun5@xiaomi.com>
|Date: Thu Dec 5 16:58:17 2024 +0800
|
| armv7-a/armv7-r/armv8-r: percpu reg store this_task
|
| This is continue work of https://github.com/apache/nuttx/pull/13726
|
| We can utilize percpu storage to hold information about the
| current running task. If we intend to implement this feature, we would
| need to define two macros that help us manage this percpu information
| effectively.
|
| up_this_task: This macro is designed to read the contents of the percpu
| register to retrieve information about the current
| running task.This allows us to quickly access
| task-specific data without having to disable interrupts,
| access global variables and obtain the current cpu index.
|
| up_update_task: This macro is responsible for updating the contents of
| the percpu register.It is typically called during
| initialization or when a context switch occurs to ensure
| that the percpu register reflects the information of the
| newly running task.
|
| Signed-off-by: hujun5 <hujun5@xiaomi.com>
Signed-off-by: chao an <anchao.archer@bytedance.com>
Summary:
- Added LLVM target definitions (`LLVM_ARCH`, `LLVM_CPU`, `LLVM_ABI`) to `arch/x86_64/src/cmake/Toolchain.cmake` and `arch/x86_64/src/common/Toolchain.defs`
- These definitions are necessary for compatibility with LLVM-based toolchains and ensure proper target architecture, CPU, and ABI settings
Impact:
- Enables support for LLVM-based toolchains when building for x86_64 architecture
- No functional changes for existing GNU-based toolchains
- Improves maintainability by centralizing LLVM-specific configurations in the toolchain files
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Summary:
- Added LLVM target definitions (`LLVM_ARCHTYPE`, `LLVM_CPUTYPE`, `LLVM_ABITYPE`) to the x86 toolchain configuration file
- These definitions are necessary for compatibility with LLVM-based toolchains
Impact:
- Enables support for LLVM toolchains when building for x86 targets
- No functional changes for existing GCC-based toolchains
- Improves cross-compilation flexibility by supporting additional toolchain options
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
ADC peripheral can be configured also for PWM trigger, so the ifdef
should depend only on CONFIG_SAMV7_AFEC_SWTRIG. Also handle the
situation when ANIOC_TRIGGER is called and the peripheral is not
configured for SW trigger (but the other one may be, so config option
is set).
Trigger values saved to the private structure are also changed to
enums for better code clarity.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
reason:
In x86_64, tcb->xcp.regs is always valid, and we obtain the location
where the context is saved through irq_xcp_regs every time an interrupt occurs.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
reason:
1 Accelerated the implementation of sched_lock, remove enter_critical_section in sched_lock and
only enter_critical_section when task scheduling is required.
2 we add sched_lock_wo_note/sched_unlock_wo_note and it does not perform instrumentation logic
Signed-off-by: hujun5 <hujun5@xiaomi.com>
add sim_rpmsg_port_uart.c to verify the rpmsg port uart wrapper layer,
The physical transport layer could be:
1. SIM_RAM_UART(current)
2. SIM_UART(through "socat" virtual "/dev/pts/*", "socat" could monitor the bus data)
Signed-off-by: chao an <anchao.archer@bytedance.com>
This removes the need to call nxsched_self upon exception return. Later
with a bit of added logic, it is possible to use tp in kernel to store and
read the current tcb.
Note: setting tp in riscv_restorecontext is too late for this, as
this_task() points to the (next) ready-to-run task, thus tp should be
updated when the rtr list is updated (via up_update_task, which does not
exist for risc-v yet)
Set the LOCKED bit when the final ddr segmentatition is
in place. Otherwise the system is prone to potential
security issues if the config is altered later. Once the
LOCKED bit is set, the register may no longer be changed.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Corrections to CA training verify step. The original copied from HSS didn't
make sense in all aspects:
- The check is not per lane, so it should be out of the "for (lane_sel" loop.
- The check wasn't proper. The expected outcome is just a vector of increasing numbers
separated enough
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
After read training, check also that the eye is centered properly. Sometimes
after the training the width is long enough, but it is not centered.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Interrupts on MPFS platform are currently served on the hart, on
which the up_enable_irq was called.
Call to up_disable_irq may execute on different hart than on which
the up_enable_irq was executed. In this case the interrupt is not
disabled currently.
While there is nothing fancy (irq affinity control or such), an
easy way to fix this is to simply disable the irq on all harts.
This also changes the prototypes of mpfs_plic_get_iebase and
mpfs_plic_get_claimbase to get the hart id as an argument, in
order to accomplish this.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
