In the toolchain, ARCH_TOOLCHAIN_XXX is used to select the compiler to be used. If clang is selected here, subsequent errors will occur
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
The tx int handler will call uart_xmitchars() to make a fake interrupt event,
but this is unsafe after enabling interrupts. This PR will add a critical section
to ensure that the txint process will not be interrupted by the IRQ
Signed-off-by: chao an <anchao.archer@bytedance.com>
AVR uses Hardward architecture with separate address space for program
memory (flash) and data memory (RAM). Normal program flow can only
access data memory which means that all variables - including const
variables - have to be copied into RAM to be accessible. (This happens
automatically during startup.)
It is possible to work around this limitation in software but that
can have severe impact on performance and/or API complexity. It is hardly
feasible to change NuttX interfaces in a way that would allow to make use
of this workaround.
On newer AVR families, there is an alternative option enabled by this patch.
These chips map part of their program memory (a 32kB window) into data
memory address space. This patch leverages this feature and adds support
for placing const variables into the mapped window. No copy to RAM is done
for them.
Const variables are therefore loaded directly from flash (not consuming
RAM) while still being available to be used by any NuttX interface.
Linker script of breadxavr board is changed to make use of these changes.
Tested by verifying string addresses - parameters in printf call
in a custom application (and also by running the application and verifying
its output.)
Documentation tested by build.
Signed-off-by: Kerogit <kr.git@kerogit.eu>
Added logic to set hasdma to false. This is needed to enable or not enable interrupts on a per ADC basis. Made other minor formatting changes.
Fixed build issues with non ADC/DMA configurations.
The architecture defines maximum of 128 interrupts, whereas previous
code only supported 32 interrupts. For every 32 interrupts added,
there are three additional registers: INTERRUPT, INTCLEAR, and INTENABLE.
This patch adds support for handling these registers.
Signed-off-by: chenxiaoyi <chenxiaoyi@xiaomi.com>
GICD_ICFGR requires full 32-bit RMW operations.
Each interrupt uses 2 bits; thus updates must be synchronized
to avoid losing configuration in concurrent environments.
RMW conflict on GICD_ICFGRn (without lock)
CPU0 (set IRQ32 edge) CPU1 (set IRQ33 level)
--------------------- -----------------------
val0 = read(ICFGRn) │ val1 = read(ICFGRn)
│
val0 |= (edge << 4) │
│ val1 &= ~(3 << 6)
│
write(ICFGRn, val0) │
│ write(ICFGRn, val1)
=> IRQ32 config lost OR IRQ33 config lost
(depends on which write finishes last)
Concurrent RMW on ICFGRn causes lost config.
Protect with spinlock to avoid data race.
Since interrupt type configuration is infrequent,
a single global GIC lock is sufficient (no need for
fine-grained locking per ICFGR register).
Signed-off-by: Shen Cao <caoshen3@lixiang.com>
Previous code was failing to disable error interrupts which
due to standard CAN retransmissions might trigger continusouly
(for example, with a disconnected CAN interface) flooding the
system and preventing other operations to continue.
Fixes: https://github.com/apache/nuttx/issues/16668
Signed-off-by: Carlos Sanchez <carlossanchez@geotab.com>
Commit 83a119160 fixed SMP by removing call to uart_xmitchars from inside spinlock.
This only works for SMP, since uart_xmitchars has a lock only in SMP. In a single
core configuration the function can be called in parallel from the interrupt
handler and from the imx9_txint.
Fix this by filling the uart buffers already before enabling the
interrupt, this way it is not possible to get the function called in parallel
for the same device.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
This commit adds the lowerhalf driver support for the I2C Slave.
While not currently ideal, it is compatible with the upperhalf i2c slave driver.
A workqueue can be used to delegate the isr work to the upperhalf driver.
But keep in mind wq introduces a lot of delay and in certain scenarios,
it is better to write your own better upperhalf driver.
Signed-off-by: Stepan Pressl <pressl.stepan@gmail.com>
This product does not have MTE. MTE is only available for Arch or higher extensions of armv8-5+memory tags
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
1. Add hw_tags.c, which will call arm64_mte to implement tagging of memory blocks by operating registers
2. It has been able to run normally on the default NX memory allocator, excluding mempool and tlsf
3. On more complex configurations, memory tests such as memstress can run normally without system crashes
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
Support hardware debugging of ARM architecture, and support smp mode.We can use "up_debugpoint_add" or "up_debugpoint_remove" to add breakpoints, and the hardware will jump into the interrupt after detecting it.
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
1. When the Clang compiler turns on "-fsanitize=kernel-address", inlining, global variables, and stack detection are enabled by default and must be turned off manually.
2. -mllvm is the parameter passing method of Clang, and --param is the parameter passing method of GCC
After the modification, KASan compilation and operation will be supported for Clang 18 and above
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
error: unpredictable STXR instruction, status is also a source
99 | "stxr %w0, %1, [%2] \n"
| ^
<inline asm>:5:10: note: instantiated into assembly here
5 | stxr w10, x10, [x9]
Using w0 to pass the result can cause the "status register is also a source" problem, resulting in unpredictable behavior.
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
