Introduce minimal chip support for the STMicro STM32N6 family
(Cortex-M55, ARMv8.1-M with TrustZone and FPU), sufficient to bring
up an NSH console over USART1.
Scope (deliberately minimal first drop):
- Chip selector ARCH_CHIP_STM32N6 wired into arch/arm/Kconfig and
chip-name mapping ("stm32n6").
- Sub-Kconfig under arch/arm/src/stm32n6 with the STM32N657X0 chip
selector and a single user-selectable USART (USART1).
- Boot path: stm32_start with a naked dispatcher that clears the
boot-ROM MSPLIM/PSPLIM stack limits before any compiler-emitted
prologue, then runs vector relocation and SRAM-only heap init.
The chip runs entirely in the Secure state; SAU is left in its
reset configuration.
- PLL1-based clock tree fed from HSI64 targeting 200 MHz CPU, with
USART1 kernel-clock routed to HSI for a predictable BRR that is
independent of any later clock change.
- Low-level USART driver with full serial framework support.
stm32_serial.c is adapted from arch/arm/src/stm32h5/stm32_serial.c
(sibling ARMv8-M Mainline port with the same USART IP), stripped
of DMA-RX, LPUART, the per-USART2..5 plumbing, RS-485 driver-enable,
TIOCSINVERT/SWAP and HALFDUPLEX paths.
- SysTick system timer.
- GPIO, PWR and RCC helpers.
TrustZone, MPU, I/D-cache and Helium (MVE) are left disabled to
minimise bring-up surface; these will be added in follow-up patches
alongside the drivers that need them.
Signed-off-by: ImBonkers <samuelnlinden@pm.me>
BREAKING CHANGE: remove PWM_MULTICHAN option
PWM_MULTICHAN option is redundant, we can just set CONFIG_PWM_NCHANNELS > 1.
At default CONFIG_PWM_NCHANNELS is set to 1, so the default behavior is preserved.
Access to single channel API is now `info->channels[0].XXX` instead of `info->XXX`
This is the first step to simplify PWM implementation and make it more portable.
Signed-off-by: raiden00pl <raiden00@railab.me>
Add support for the i.MX9 SAR ADC block.
The driver provides initialization, deinitialization, channel-mask
validation, and one-shot reads for the supported ADC channels. It also
handles the ADC clock bring-up, power-up sequence, calibration, and raw
12-bit result extraction from the per-channel data registers.
Signed-off-by: Joonas Ihonen <joonas.ihonen@tii.ae>
The goal is to only execute recipes when there is an actual change in
the prerequisites.
There are several issues which cause the nuttx binary target to be
re-made every time the top level make is run.
1. Previously the target nuttx$(EXEEXT), was used, but make resolved
this in the relative directory make -C $(ARCH_SRC), and couldn’t find
it (need an absolute path: `$(TOPDIR)/..).
2. The .tmp prerequisite for nuttx was always deleted
3. libboard's recipe had a sub-make which may or may not update that
target. This was a phony target, and was therefore always considered out
of date.
These issues were causing the nuttx recipe to be run every make, which
was hiding some missing prerequisites:
1. the .config is a prerequisite for the .tmp target
2. libapps.a (and other linklibs) are pre-requisites for nuttx
Changes:
The changes are only in the build system, and only for arm.
Track nuttx$(EXEEXT) via vpath so Make knows when it's already up to
date without an explicit path. Add $(TOPDIR)/.config as a dependency
to the linker script preprocessing so config changes trigger
re-preprocessing.
Keep the .tmp linker script on disk (clean already removes it) so
timestamp-based dependency checking works across builds. These .tmp
files need to be added to the gitignore or the CI will complain.
Use FORCE pattern for board/libboard to ensure it's always checked
but use the actual library file as the link dependency so nuttx is
only re-linked when library content changes. Add staging libs as
dependency to nuttx link rule so changed app libs trigger re-link.
Signed-off-by: Liam Hickey <williamhickey@geotab.com>
The sim/src/nuttx-names.in symbol-rename list is the mechanism that
keeps every nuttx libc function used inside nuttx.rel from clashing
with the same-named function in host glibc when the sim executable
is finally linked. The list already covers ~200 symbols (memcpy,
strlen, strcat, strchr, ...) but memchr was missing.
On x86_64 Linux hosts the omission has no visible effect because
host glibc dispatches memchr through an IFUNC resolver
(__memchr_ifunc) that the static libc.a path does not eagerly pull
in for typical sim links. On HOST_ARM64 (Ubuntu 20.04 aarch64,
glibc 2.31 .. 2.41), however, the final cc/ld invocation in the
sim Makefile drags libc.a(memchr.o) into the link, which then
collides with nuttx libc's lib_memchr.o that has already been
folded into nuttx.rel:
/usr/bin/ld: /usr/lib/gcc/aarch64-linux-gnu/9/../../../aarch64-linux-gnu/libc.a(memchr.o):
in function `__memchr_ifunc':
(.text+0x0): multiple definition of `memchr';
nuttx.rel:libs/libc/string/lib_memchr.c:55: first defined here
Add memchr to the rename list (placed in alphabetical position
between malloc_usable_size and memcpy). After this fix sim:nsh
builds cleanly on aarch64 Linux hosts (verified on NVIDIA Jetson
Orin L4T Ubuntu 20.04 + Raspberry Pi 4B Debian 13 trixie). The
behaviour on x86_64 / macOS / Cygwin hosts is unchanged because
those targets either never hit the collision or use the
underscore-prefixed variant gated by NXSYMBOLS macro definition
in the same file (lines 26-31).
Signed-off-by: Jinji Cui <113000688+cjj66619@users.noreply.github.com>
The STM32 DMA NDTR/CNDTR transfer-count register is 16 bits wide on
every STM32 series the in-tree driver supports (IPv1 CNDTR, IPv2
SxNDTR). spi_exchange()'s DMA path forwarded the caller's full
nwords to stm32_dmasetup(), so a single SPI_EXCHANGE() of >= 65536
words silently programmed NDTR to (nwords & 0xffff). When the
truncated count was zero - the typical case for an exact 64 KiB
transfer (flash erase block, FAT cluster, common DMA staging
buffer) - the stream completed instantly with no transfer-complete
interrupt and the caller deadlocked in spi_dmarxwait().
Walk the request in chunks of at most 65535 words inside the
existing DMA branch, reusing the same spi_dma{rx,tx}{setup,start,
wait}() sequence per chunk. Single-descriptor transfers (every
in-tree caller today) are byte-for-byte identical. CONFIG_SPI_TRIGGER
is honored for the first chunk only; subsequent chunks must run
unconditionally because re-arming between chunks of one logical
exchange was never part of the SPI_TRIGGER contract.
Drive-by: rescale priv->buflen-clamped nwords so the DMA
descriptor matches the actually-copied byte count, promote the
spiinfo() format specifier from %d to %zu, and fix two adjacent
comment typos.
See the PR description for reproduction, NSH log and benchmark
numbers (5.12 MB/s, 97.5% of SCK/8 @ 42 MHz on STM32F407 + W25Q128).
Signed-off-by: Jinji Cui <113000688+cjj66619@users.noreply.github.com>
This commits enables moving BSS data segments to the external PSRAM
on ESP32-P4. This is controlled by a Kconfig option.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
PendSV is the deferred half of the Cortex-M context-switch path: a
higher-priority ISR that wakes a task sets PendSV pending and returns,
and PendSV then performs the register save/restore. This pattern is
only safe when PendSV runs at the lowest priority - otherwise a
peripheral ISR can preempt the context switch mid-update and corrupt
thread state.
The previous write of DEFPRIORITY32 to NVIC_SYSH12_15_PRIORITY in
up_irqinitialize() leaves PendSV at NVIC_SYSH_PRIORITY_DEFAULT (0x80),
the same priority as peripheral IRQs. Read-modify-write the SHPR3 to
lower only the PendSV byte to NVIC_SYSH_PRIORITY_MIN.
This is the canonical ARM Cortex-M priority arrangement and it matches
e.g. this reference:
https://nuttx.apache.org/docs/latest/guides/zerolatencyinterrupts.html (although
worked with a three-bit priority system)
This patch hardens up_irqinitialize against future peripheral-IRQ
prioritisation.
Signed-off-by: Daniel Fanache <dan@rts.ro>
At system startup, the NVIC was configured for proper default priority
only for the first three IPR registers, even though the loop was
executed 13 times - due to a gotcha on what the `NVIC_IRQ_PRIORITY(i)`
macro returns.
IRQs 12-51 stayed at the reset priority of 0 - highest in the system;
so any peripherals issuing those interrupts will shoot through
critical sections that rely on
BASEPRI = NVIC_SYSH_PRIORITY_DEFAULT (0x80).
This can corrupt the TCB ready-to-run list and semaphore wait queues;
this is hard to reproduce (e.g. in ostest) because it requires a
peripheral ISR to land inside a critical section, but the failure
modes range from hangs to wild pointer crashes once it does.
In my case I had SPI and I2C peripherals that were issuing IRQs and
were preempting scheduler and semaphore list operations, causing
corruption.
Step the loop by four and bound it with RP23XX_IRQ_NEXTINT so every
IPR covering IRQs 0..51 is written once with DEFPRIORITY32.
Signed-off-by: Daniel Fanache <dan@rts.ro>
Adapt the macOS AVFoundation backend for multi-device discovery,
camera index mapping and capture startup compatibility. This enables
reliable use of multiple cameras through the SIM camera framework.
Signed-off-by: Peter Bee <bijunda@bytedance.com>
Allow the SIM camera/V4L2 capture framework to manage multiple
imgdata instances with dynamic mounting. This avoids cross-talk
between camera streams when multiple devices are used.
Signed-off-by: Peter Bee <bijunda@bytedance.com>
The host interrupt callback was incorrectly using the wrong IRQ for
disconnected. In host mode the same IRQ is used for connect/disconnected
and it must check a status bit to know which one.
When a USB device was unplugged, the host channels were free'd,
but if they happen to be mid-transfer, that transfer was never cancelled
so the USB hardware might still be trying to perfrom a transfer after
was free'd. Fixed by cancelling any transfers on free.
Signed-off-by: daniellizewski <daniellizewski@geotab.com>
After recent changes on the event handler for the RISC-V-based
Espressif SoCs, the same set of changes were ported back to xtensa
devices.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
This commit enables the ethernet driver support on ESP32-P4 based
on a common-source implementation. This required a set of changes
regargind the event handler for the Wi-Fi driver (which is now
shared with the ethernet driver).
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Use GPIO_MODE_INPUT for STM32F1 pinmap entries that are configured as
GPIO_INPUT instead of carrying GPIO_MODE_2MHz.
For STM32F1 the MODE field selects output speed only for output or
alternate-function output pins. stm32_configgpio() forces input pins to
input mode regardless of the encoded MODE bits.
From arch/arm/src/stm32/stm32_gpio.c:
311 /* Decode the mode and configuration */
312
313 regval = getreg32(cr);
314
315 if (input)
316 {
317 /* Input.. force mode = INPUT */
318
319 modecnf = 0;
320 }
321 else
322 {
323 /* Output or alternate function */
324
325 modecnf = (cfgset & GPIO_MODE_MASK) >> GPIO_MODE_SHIFT;
326 }
Signed-off-by: raiden00pl <raiden00@railab.me>
NuttX uses Quadrature Encoder lower half driver to internal QE from
MCUs and also with Magnetic Rotary Encoder sensors. But when the
STM32 QE is not enabled, the board code will try to compile the
stm32_qencoder.c because Magnetic Rotary Encoders enables the
CONFIG_SENSORS_QENCODER. This patch fixes this issue.
Signed-off-by: Alan C. Assis <acassis@gmail.com>
The planar copy was used even when linar mode was used (chain4 = 1)
Probably this modification could impact VGA text mode, but for now
it is not important, since the goal is get graphic mode working.
Signed-off-by: Alan C. Assis <acassis@gmail.com>
BREAKING: In an effort to simplify NuttX initialization, NSH_ARCHINIT is
removed. board_app_initialize is also removed. BOARD_LATE_INITIALIZE now
performs all board initialization logic, and is by default enabled. All
references to these symbols are removed. BOARDIOC_INIT remains, but will
result in -ENOTTY when called. It is to be removed in a later commit.
Quick fix: Boards relying on NSH_ARCHINIT should now enable
CONFIG_BOARD_LATE_INITIALIZE instead. If the application needs
fine-grained control over board initialization from userspace, the logic
performed by BOARDIOC_INIT may be copied to the board_finalinitialize
function and used instead via BOARDIOC_FINALINIT. All
board_app_initialize logic provided by NuttX is now moved to
board_late_initialize, and the same should be done for out-of-tree
boards.
Signed-off-by: Matteo Golin <matteo.golin@gmail.com>
The register index layout for D16-D31 and FPU_CONTEXT_REGS was guarded
by CONFIG_ARM_HAVE_DPFPU32 (hardware capability) in three header files,
but all save/restore code in the corresponding .S files gates on
CONFIG_ARM_DPFPU32 (software enable).
These two macros are distinct:
CONFIG_ARM_HAVE_DPFPU32 - set by chip via 'select'; means hardware
has D16-D31 registers
CONFIG_ARM_DPFPU32 - user-selectable; means software has chosen
to use D16-D31 (requires hardware support)
When ARM_HAVE_DPFPU32=y and ARM_DPFPU32=n, the header defined
REG_FPSCR at offset 64 and FPU_CONTEXT_REGS=65, while the assembly
only saved S0-S31+FPSCR (33 words), placing FPSCR at offset 32.
This mismatch causes incorrect register access and wrong xcptcontext
sizing.
Signed-off-by: yaojiaqi <yaojiaqi@lixiang.com>
In esp_espnow_pktradio.c, after ESP-NOW is successfully initialized in espnow_ifup, call netdev_carrier_on(dev).
In espnow_ifdown, call netdev_carrier_off(dev).
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
Create a bidirectional dshot lower-half driver, using the flexio block.
This driver enables use of DShot protocol for Electronic Speed Controllers
(ESCs) typically used in drone motor control.
Eight channels of DShot per flexio block are supported in:
- Normal mode in all DShot speeds, with telemetry request (uart response
needs to be handled outside of this driver)
- Bidirectional mode in all DShot speeds, with telemetry request & response
- Configurable to use either independent TX timers for each channel, or to
use a common TX timer for all channels to synchronize the output
- For bidirectional RX, each channel always uses an own timer.
In normal mode, the driver operates without any interrupts.
In bidirectional mode, the driver reconfigures the FlexIO timers (as needed)
and shifters from TX to RX in the interrupt handler, and reads out the
raw response packet.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
This modify just modify the function to let the user that the function
failed to initialize the VGA mode.
Signed-off-by: Alan C. Assis <acassis@gmail.com>
DLASTSGA needs to be offest for TCM backdoor address.
Cleanup as well using inline helper for calculuation.
Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
Always allocate per-file can_reader on open so write-only descriptors get msgalign / ioctl state; free that context on close when it was never linked into cd_readers (fixes leak).
Cap each drain loop (20×500 ms) so close() cannot block forever when bxCAN retries without ACK or dev_txempty never clears.
Fix stm32can_vputreg debug log to print the written value (correct parameter name).
Signed-off-by: Alexey Matveev <tippet@yandex.ru>
The simulated time ratio feature introduced a host_set_timeratio()
call in sim_head.c, but the Windows host time implementation was
missing this symbol, causing a link error. Add a no-op stub since
the time ratio feature is not implemented on Windows.
Signed-off-by: Lingao Meng <menglingao@xiaomi.com>
dispatch_walltime() expects a delta in nanoseconds from now, but the
previous code subtracted CLOCK_REALTIME from a CLOCK_MONOTONIC absolute
timestamp, which have different epochs and produce a meaningless result.
Fix by subtracting the current CLOCK_MONOTONIC absolute time to get the
correct remaining duration.
Signed-off-by: Lingao Meng <menglingao@xiaomi.com>
Add CONFIG_SIM_WALLTIME_RATIO Kconfig option and --sim-rt-ratio=
command-line argument to control the ratio of simulated time to
real time in percent. 100 means real-time (default), 200 means
simulated time advances twice as fast, 50 means half speed.
The implementation applies the ratio in host_gettime(), host_sleepuntil()
and host_settimer() so both SIM_WALLTIME_SLEEP and SIM_WALLTIME_SIGNAL
modes are supported.
This is inspired by the --rt-ratio feature in Zephyr's native_sim board.
Tested on sim:nsh with the following sleep test:
$ echo -e "sleep 2\nexit" | time ./nuttx
real 0m2.0xxs
$ echo -e "sleep 2\nexit" | time ./nuttx --sim-rt-ratio=200
real 0m1.0xxs
$ echo -e "sleep 2\nexit" | time ./nuttx --sim-rt-ratio=50
real 0m4.0xxs
Signed-off-by: Lingao Meng <menglingao@xiaomi.com>
In sporadic cases it is possible that a SPI exchange returns stale RX data from the DCACHE.
This occurs when:
- DCACHE is enabled
- DMA is used
The impact of this can be hard to debug and vanishes when the timing even changes minimally.
This is caused by the DCACHE being invalidated before the actual DMA transaction starts which violates
the recommendations from AN4839 and also does not match the implementation of other drivers on the STM32H7/STM32F7.
Fixed by invalidating the DCACHE right before the actual read, which matches the implementation
of the STM32F7 SPI driver.
Signed-off-by: alexcekay <alexander@auterion.com>
The PR #18654 removed the Kconfig option `RMT_LOOP_TEST_MODE` used
by Espressif's RMT peripheral. This commit reintroduces it as a
lower-half driver interface used to enable internal loopback tests.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Enable USART3 support for STM32F412 and use it as the default NUCLEO-F412ZG nsh console path.
The ST-LINK virtual COM port on this board is wired to USART3 on PD8/PD9. Restore USART2 to its header-pin routing, switch the nsh defconfig to USART3, and update the board documentation to match the shipped solder-bridge configuration described in issue #17722.
Signed-off-by: aviralgarg05 <gargaviral99@gmail.com>
- Moved the creation of the `nxtmpdir` folder for third-party packages to the root `CMakeLists.txt` file.
cmake/nuttx_3rdparty.cmake
- Add the nuttx_remove_nxtmpdir function to remove the third-party cache directory under nuttx/../nxtmpdir
Signed-off-by: simbit18 <simbit18@gmail.com>
