chip/efm32_start.c:150:3: warning: implicit declaration of function 'itm_syslog_initialize';
did you mean 'syslog_initialize'? [-Wimplicit-function-declaration]
150 | itm_syslog_initialize();
| ^~~~~~~~~~~~~~~~~~~~~
| syslog_initialize
Signed-off-by: chao an <anchao@lixiang.com>
Summary:
- In https://github.com/apache/nuttx/pull/14465,
atomic_compare_exchange_weak_explicit() was newly introduced
in semaphore. However, cxd56xx has an issue with the API
if SMP is enabled (see up_testset2 in cxd56_testset.c).
- This commit fixes the issue by using LIBC_ARCH_ATOMIC.
Impact:
- Only cxd56xx SoCs in SMP mode.
Testing:
- Tested with spresense:smp, spresense:wifi_smp
- NOTE: If DEBUG_ASSERTIONS is enabled assert would be happend.
I think this might be another issue.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
time/lib_localtime.c: In function 'tz_lock':
time/lib_localtime.c:396:7: error: 'tpidr_el1' undeclared (first use in this function)
396 | if (up_interrupt_context() || (sched_idletask() && OSINIT_IDLELOOP()))
| ^~~~~~~~~~~~~~~~~~~~
Signed-off-by: ligd <liguiding1@xiaomi.com>
The PLL clock configuration was simplified on the assumption the clocks are correctly set in the board.h file. Instead of seperate conditions
for register components, assume the relevant PLL registers are fully defined in board.h. This should result in easier to understand defines in board.h
and simpler code flow in the standard clock configuration function.
Changes were mad in the board file alongside changing the arch files. Changes to board/stm32h5:
- PLL1 has been configured to use integer instead of fractional mode to reach the 250 MHz target. PLL2 and PLL3 configurations were
removed since they are currently unused in the H5 configuration.
- PLL1 output was verified by testing for changes in serial baud rate.
syslog_putc() have a lot of duplicate logic with syslog_write().
remove syslog_putc() and reuse syslog_write() to simplify syslog printing.
Signed-off-by: chao an <anchao@lixiang.com>
reason:
When entering an exception or interrupt, there are two sets of registers:
one is the "running regs", which we need to save,
and the other is the "ready to running regs", which we may soon use.
For consistency in logic, we can always store the "running regs" in the regs field of g_running_tasks,
otherwise it may lead to errors in the storage location of the "running regs."
When we need to access the "running regs," we should uniformly retrieve them from the regs field of g_running_tasks.
As the next step, we will rename the set_current_regs/up_current_regs functions
for each architecture to more appropriate names, solely for the purpose of identifying interrupts.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Some armv7-m-based SoCs do not work with atomic instructions,
even though armv7-m supports them.
To avoid using atomic instructions generated by gcc,
CONFIG_LIBC_ARCH_ATOMIC is newly introduced with which
arch_atomic.c is linked explicitly.
However, the function names need to be changed to avoid
build errors, since the functions described in stdatomic.h
are gcc built-in and inlined when the code is compiled.
About libcxx with CONFIG_LIBC_ARCH_ATOMIC, it still
does not work. It is also needed to call nx_atomic_ ver
instead of __atomic ver in
libcxx/include/__atomic/cxx_atomic_lmpl.h.
Signed-off-by: Takuya Miyasita <Takuya.Miyashita@sony.com>
This performs the DDR training for imx93-evk. In addition to the source code,
it downloads binaries which are included in the final image. The bootloader
must be ARCH_CORTEX_A53 instead of A55 due to atomic instructions that don't
work with the OCRAM / EL3 combination.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
This commit adds a max_pins field into the private struct.
AFEC0 has 11, AFEC1 has 12. The 12th pin of AFEC0 is an internal
pin connected to a temperature sensor, which we don't use.
Signed-off-by: Stepan Pressl <pressste@fel.cvut.cz>
1. arch/arm/src/cmake/gcc.cmake: The same judgment has been made in line 164
2. boards/sim/sim/sim/scripts/Make.defs: arch/sim/src/Makefile also has in line 147
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
Added I2C driver for the STM32H5. This driver uses the STM32H7 I2C driver as a base. The primary difference is setclock dynamically sets the I2C TIMINGR register instead of using hardcoded values. This allows the I2C peripherals to use any of the input clocks and set to any speed 0-1MHz. Additionally, Kconfig options were made available to set the Digital Noise Filter (DNF), Analog Noise Filter, I2C Clock source (i2c_ker_ck), as well as set i2c rise/fall times which are crucial to timing. Care must be taken when setting the clock source and filters, as not all settings are compatible with all i2c clock frequencies.
Trdc is configured in EL3 bootloader
Clock pre-initialization is also executed there.
Trdc board configuration for imx93evk included
Signed-off-by: Jouni Ukkonen <jouni.ukkonen@unikie.com>
In https://github.com/apache/nuttx/pull/13044,
LIBC_ARCH_ATOMIC was finally removed.
Howerver, the following chips still have the config.
- ARCH_CHIP_ESP32S3
- ARCH_CHIP_ESP32C3_GENERIC
- ARCH_CHIP_ESP32H2
This commit fixes the issue.
1. Excerpted from: https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/blob/main/samples/src/cpp-baremetal-semihosting-prof/proflib.c
2. Since llvm profile supports more than just gcov, and some features have not yet been explored, two clang gcov implementations are supported after this patch
3. Using this lib only supports the gcov compilation options of "-fprofile-instr-generate -fcoverage-mapping"
4. This file is heavily dependent on the compiler clang version, and is currently aligned with ci, supporting 17.0.1 and below. 18 and above are not supported by this library due to different internal implementations of the compiler
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
`ARCH_HAVE_RAMFUNCS` has no actual effect on the ESP32-C3,
but ESP32-C3 has RAM functions, so select it to mark that is OK,
and then we can also suppress the RWX memory region warning.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Some armv7-m-based SoCs do not work with atomic instructions,
even though armv7-m supports them.
To avoid using atomic instructions generated by gcc,
CONFIG_LIBC_ARCH_ATOMIC is newly introduced with which
arch_atomic.c is linked explicitly.
However, the function names need to be changed to avoid
build errors, since the functions described in stdatomic.h
are gcc built-in and inlined when the code is compiled.
Signed-off-by: Takuya Miyasita <Takuya.Miyashita@sony.com>
Suppress the warning message "nuttx has a LOAD segment with RWX permissions" in case of RAM boot mode is selected.
RAM MODE: BOOT_RUNFROMEXTSRAM/BOOT_RUNFROMISRAM/BOOT_RUNFROMSDRAM/BOOT_COPYTORAM
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
when we build mbedtls in vela with ghs compiler, the mbedtls need to
access __ARM_ARCH and __ARM_FEATURE_DSP, and to construct the inline asm
code based on these two macros.
With ghs compiler, these two macros are not defined, and will be
evaluated as 0 by default, and thus will using to wrong inline asm code,
in order to handle this issue, we need to add conversion between the ghs
and gcc with __ARM_ARCH, __ARM_FEATURE_DSP
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
when build with greenhills_202354, the naked_function should only
contains the basic asm statements, so if the naked_function contains the
statements that using to accept params from C lang runtime, then build
error will reported:
error #101112: Only basic asm expressions are allowed for functions
with __attribute__((naked)): dispatch_syscall
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
This commit adds files in preperation of adding ethernet drivers for the STM32H563 and Nucleo-H563ZI board.
It also modifies the pinmap to include ethernet pins (and cleaned up leftover comments from L5 file), as well as
add those pins to the board.h for the nucleo-h563zi.
Files added:
- arch/arm/src/stm32h5/hardware/stm32_ethernet.h
- arch/arm/src/stm32h5/hardware/stm32_sbs.h
- Not fully implemented, just register necessary for ethernet driver.
The naming scheme in board.h changed from STM32H5_ to STM32_. As a result we needed to adjust the naming of the STM32H5_BOARD_USExxx variables in stm32h5xx_rcc.c. Also made changes to allow the enabling of all 3 of HSI, CSI, or HSE in stm32_stdclockconfig. Lastly, the HSIDIV bits in RCC_CR were not being cleared before being set. Added logic to clear these bits.
defined CSIRDY_TIMEOUT
There is an enormous error in the system call dispatch logic; if a task
is inside a critical section (local interrupts disabled) there is a chance
that during a context switch when the task resumes, local interrupts are
erroneously ENABLED. This obviously leads to unexpected crashes and such.
This happens when the CPU status has Previous Interrupt Enable (PIE) set
to 1, even though Interrupt Enable (IE) is set to 0.
When the system call returns via ERET, the CPU sets PIE->IE and if PIE=1
interrupts get enabled.
This is fixed easily by explicitly CLEARING PIE from the register save
area, if IE=0 when the system call was started.
In the virtualized environment, each time an SGI is sent, the value of IGROUPR0 needs to be read once. Since the GIC Redistributor is a purely emulated device, each read of IGROUPR0 will cause a VM exit, causing serious performance degradation. This patch replaces the read with the value previously set in `gicv3_cpuif_init`, and we assume that this value has not been modified after initialization.
Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
