Commit graph

904 commits

Author SHA1 Message Date
Matteo Golin
590678ec96 boards/esp32c3-xiao: Fix ble configuration crash
Removes CXX initialization from the 'ble' configuration, preventing it
from crashing at boot time.

Signed-off-by: Matteo Golin <matteo.golin@gmail.com>
2026-01-14 18:43:53 +01:00
Matteo Golin
a22e26924d cmocka/defconfig: Update defconfigs to include cmocka application
The cmocka test framework is compiled as a library by default in
(apache/nuttx-apps#3270), and does not include the cmocka application
binary unless CONFIG_TESTING_CMOCKA_PROG=y. This commit updates the
defconfigs which include cmocka to also compile the cmocka binary, which
is the behaviour they were created with.

Signed-off-by: Matteo Golin <matteo.golin@gmail.com>
2026-01-12 10:15:00 +08:00
Huang Qi
8b3862d19b style: Fix case statement formatting in power management callbacks.
Remove unnecessary parentheses around case labels in switch statements
for power management callback functions. This fixes checkpatch style
violations for case statement formatting.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2026-01-10 12:59:14 -03:00
p-szafonimateusz
cb87a19d7d boards/rv-virt/citest: migrate to NTFC
migrate rv-virt/citest to NTFC test cases

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2026-01-05 22:03:01 +08:00
p-szafonimateusz
5585b01636 boards/rv-virt/citest64: migrate to NTFC
migrate rv-virt/citest64 to NTFC test cases

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2026-01-05 22:03:01 +08:00
p-szafonimateusz
b88f86ba5d boards/citest: rename run scripts to run.sh
Executable files called "run" don't pass checkpath verification,
so we change the name to "run.sh"

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2026-01-04 09:40:12 -03:00
Eren Terzioglu
cb62a59d19 boards/risc-v/esp32c6: Add coremark defconfig
Add coremark defconfig for esp32c6-devkitc

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2026-01-01 17:03:20 +08:00
Justin Erenkrantz
7298977894 risc-v/litex: Add 64-bit S-mode vexiiriscv support for litex.
Most of the peripheral support matches litex vexriscv-smp.

* arch/risc-v/Kconfig: Defer RV32 selection to core as litex board can do RV64.
* arch/risc-v/src/litex/Make.defs
  arch/risc-v/src/litex/hardware/litex_clint.h
  arch/risc-v/src/litex/hardware/litex_memorymap.h
  arch/risc-v/src/litex/hardware/litex_plic.h
  arch/risc-v/src/litex/litex_irq.c
  arch/risc-v/src/litex/litex_irq_dispatch.c: Add CONFIG_LITEX_CORE_VEXIIRISCV
  conditional where vexriscv_smp conditionals are.
* boards/risc-v/litex/arty_a7/configs/nsh-vexii/defconfig: New config.
* boards/risc-v/litex/arty_a7/include/vexii_irq.h: vexiiriscv irq defintion.
* boards/risc-v/litex/arty_a7/include/vexii_memorymap.h: vexiiriscv memory map.
* boards/risc-v/litex/arty_a7/scripts/ld.script: Define __global_pointer for
  toolchain happiness matching other RISC-V linker scripts.

(This commit was written with assistance from Claude Code.)

Signed-off-by: Justin Erenkrantz <justin@erenkrantz.com>
2025-12-30 10:18:57 -03:00
rongyichang
3d0f6fcbad boards/risc-v: Add lvgl64_vector configuration for RISC-V QEMU
Add new RISC-V 64-bit QEMU configuration with:
- 64-bit RISC-V (RV64) architecture support
- RISC-V Vector Extension (RVV/V-extension) enabled
- LVGL graphics framework integration
- VirtIO GPU and input device support
- NSH shell with built-in applications

This configuration enables developers to build and test LVGL graphical
applications on 64-bit RISC-V targets with Vector extension support,
providing a foundation for future SIMD optimization work.

Includes:
- defconfig: Complete configuration file with all necessary options
- Updated index.rst: Build and run instructions with QEMU launch command

Signed-off-by: rongyichang <rongyichang@xiaomi.com>
2025-12-24 09:44:01 +08:00
simbit18
946bd2b36e boards/risc-v/esp32c3: add Waveshare ESP32-C3-Zero
- Add initial support for Waveshare ESP32-C3-Zero.

Signed-off-by: simbit18 <simbit18@gmail.com>
2025-12-19 07:14:22 +08:00
Yanfeng Liu
7ea747024d board/rv-virt: add elf config
This adds `rv-virt/elf` following `maix-bit/elf` to check
relocatable ELF feature.

Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
2025-12-16 13:07:37 -03:00
zhanghongyu
aa8ffea3cf netdev_upperhalf: convert Kconfig to variable
Upperhalf supports multiple working modes at the same time,
which is specified by NIC when register

Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
2025-12-14 10:01:22 +08:00
simbit18
846f86e011 boards/risc-v/esp32c3: Corrected the names of #include guards
Corrected the names of #include guards

boards:

- esp32c3-devkit

- esp32c3-legacy

Signed-off-by: simbit18 <simbit18@gmail.com>
2025-12-11 09:16:14 +08:00
Filipe Cavalcanti
1218ecfd88 boards/risc-v/esp32c3: deprecate esp32c3 boards based on esp32c3-legacy arch
This change makes the esp32c3-generic the main esp32c3 supported board: esp32c3-devkit.
The now esp32c3-legacy is pure register based and not maintained anymore.
Now, esp32c3-devkit shares the same driver implementation as ESP32-C6 and ESP32-H2.

- esp32c3-devkit  -> esp32c3-legacy
- esp32c3-generic -> esp32c3-devkit

Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
2025-12-03 13:45:13 +08:00
Filipe Cavalcanti
ea1d59e89c boards/risc-v/esp32c6: add capture example to capture defconfig
Add missing PWM capture example from the capture defconfig of
esp32c3-devkitc.

Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
2025-12-03 13:44:25 +08:00
Eren Terzioglu
8902e511d3 boards/risc-v/esp32[-c3|-c6|-h2]: Add deep sleep board support
Add deep sleep board support for risc-v based Espressif chips

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-11-29 14:35:34 +08:00
Eren Terzioglu
d4c76b1f60 arch/risc-v/esp32[-c3|-c6|-h2]: Add deep sleep support
Add deep sleep support for risc-v based Espressif devices

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-11-29 14:35:34 +08:00
Eren Terzioglu
3281721742 boards/risc-v/esp32[-c3|-c6|-h2]: Add PM board support
Add PM board support for esp32[-c3|-c6|-h2]

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-11-29 14:35:34 +08:00
v-tangmeng
34a2f0cc40 boards/arm: refresh the defconfig
This commit refreshed the defconfig.

Signed-off-by: v-tangmeng <v-tangmeng@xiaomi.com>
2025-11-24 19:43:07 +08:00
Filipe Cavalcanti
caa3772d50 boards/risc-v/esp32c3: remove CXX initialization from BLE defconfig
Espressif common initialization and lib_cxx_initialize are having
conflicts and multiple linker script issues.
Removing CXX_INITIALIZE solves those problems with no side effects.

Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
2025-11-14 23:53:14 +08:00
wangchengdong
26af1fadc9 arch: Enable event module for pcduino-a10 and smartl-c906
Enable the event module on pcduino-a10 and smartl-c906 boards
   to allow event tests to be executed on both ARM and RISC-V
   architectures.

Signed-off-by: Chengdong Wang <wangchengdong@lixiang.com>
2025-11-04 21:43:59 +08:00
haitomatic
e7ad870f18 arch/risc-v/mpfs: Add MSS CAN driver.
Refactor to  become lower half driver.

Signed-off-by: Hai To <hai.to@tii.ae>
2025-11-03 17:14:53 -03:00
haitomatic
967238ba2c arch/risc-v/mpfs: Add MSS CAN driver.
The Nuttx MSS CAN driver has an exclusive interface to the integrated MSS CAN peripheral residing in Polarfire SoC FPGAs. There are two CAN block 0 and 1 that can be configured for use. In normal mode (non AMP), CAN0 and CAN1 block base register addresses are 0x2010C000UL and 0x2010D000UL.

Signed-off-by: Hai To <hai.to@tii.ae>
2025-11-03 17:14:53 -03:00
simbit18
0625efa965 boards/risc-v: nxstyle fix Relative files path
- fix Relative file path does not match actual file.

Signed-off-by: simbit18 <simbit18@gmail.com>
2025-10-29 22:04:25 +08:00
Filipe Cavalcanti
4ccae59e69 arch/risc-v: update SPI Flash driver for ESP32-C3|C6|H2
Updates the SPI Flash driver used for user storage MTD.
Updates board linker script and bring up.

Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
2025-10-29 09:44:55 -04:00
Filipe Cavalcanti
fb4274187b boards/risc-v: optimize linker script IRAM section
Adds lipbb (Wi-Fi related) to IRAM and removes unnecessary E-Fuse sources.

Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
2025-10-23 20:34:59 +08:00
simbit18
fc536babfa board/risc-v/rp23xx-rv: Added CMake build for Raspberry Pi Pico 2 RISC-V board
- CMake added board Raspberry Pi Pico 2 RISC-V

- Created a file rp23xx_common_pico.h with function
   prototype

     int rp23xx_dev_gpio_init(void);

 to allow cmake + ninja to build without errors.

Signed-off-by: simbit18 <simbit18@gmail.com>
2025-10-22 09:01:39 -04:00
Eren Terzioglu
11b1361a96 boards/risc-v/esp32[c6]: Add multiple ULP bin board support for esp32c6
Add multiple ULP bin board support for esp32c6

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-10-21 06:32:32 -03:00
Tiago Medicci Serrano
fcb96babc5 risc-v/espressif/spi: Update common source code functions
Updates the common source code for the SPI peripheral used by
Espressif's RISC-Vs SoCs. This enables newer SoCs to be supported
in the future while maintaining backwards compatibility.

Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
2025-10-21 01:03:36 +08:00
Tiago Medicci Serrano
1519d6c80b risc-v/espressif/i2c: Update common source code functions
Updates the common source code for the I2C peripheral used by
Espressif's RISC-Vs SoCs. This enables newer SoCs to be supported
in the future while maintaining backwards compatibility.

Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
2025-09-27 21:43:33 +08:00
Tiago Medicci Serrano
f6a051ab2f boards/esp32[c3|c6|h2]: Fix GPIO function used by the button
This commit fixes the function to select the GPIO behavior for the
pins associated to the board's button.

Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
2025-09-24 14:18:46 +08:00
Tiago Medicci Serrano
851f1fd439 boards/risc-v/esp32[c3|h2]/<board>: Unset -Werror flag by default
The `-Werror` flag should be set - if needed - to `EXTRAFLAGS` var
when compiling NuttX.

Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
2025-09-23 14:17:56 +02:00
Tiago Medicci Serrano
1fb7899a01 risc-v/espressif: Remove duplicated Kconfig entry ESPRESSIF_<chip>
The Kconfig entry `ESPRESSIF_ESP32[C3|C6|H2]` can be removed as the
already existing `ARCH_CHIP_ESP32[C3_GENERIC|C6|H2`] fulfills its
purpose completely.

Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
2025-09-22 15:34:06 -04:00
Filipe Cavalcanti
a729534e52 boards/risc-v: add support for init script on ESP32-C3|C6|H2
Adds support for init script on ESP32-C3|C6|H2.

Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
2025-09-19 07:18:54 -03:00
michal matias
6eef3880a0 boards/risc-v/esp32c6: Add support for the OA-TC6 10BASE-T1x MAC-PHYs
Add support for the OA-TC6 10BASE-T1x driver to the ESP32-C6 boards.

Signed-off-by: michal matias <mich4l.matias@gmail.com>
2025-09-18 08:17:35 -03:00
Eren Terzioglu
092d7eac73 boards/risc-v/esp32c6: Add RTC GPIO board support for esp32c6
Add RTC GPIO board support for esp32c6

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-09-11 10:57:18 +02:00
Eren Terzioglu
4c03284a7d boards/risc-v/esp32c6: Add lpcore support
Add lpcore board support for esp32c6

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-09-11 10:57:18 +02:00
Filipe Cavalcanti
c15521af91 boards/risc-v: update board and defconfigs for Wi-Fi on ESP32-C3|C6
Updates the defconfigs and board source to support driver refactor.

Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
2025-08-28 21:52:03 +08:00
michal matias
76c2038d97 boards/risc-v/esp32c6: Remove board support for the NCV7410
The NCV7410 driver will be replaced. This commit removes current support for
the NCV7410 driver from the board level.

Signed-off-by: michal matias <mich4l.matias@gmail.com>
2025-08-25 20:32:35 +08:00
Serg Podtynnyi
2437771de5 boards/risc-v/rp23xx-rv/common: update board reset via BOOTROM functions
Update board reset with BOOTROM functions calls
 - normal reboot
 - reboot to bootloader

normal reboot and reboot bootloader now possible from nsh

Signed-off-by: Serg Podtynnyi <serg@podtynnyi.com>
2025-08-16 08:56:21 -03:00
Eren Terzioglu
680abacd1f boards/risc-v: Revert mdtblock initialization for esp32[-c3|-c6|-h2]
boards/risc-v: Revert mdtblock initialization for risc-v based Espressif devices

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-08-15 16:42:46 -03:00
Jukka Laitinen
d62e500940 boards/risc-v/mpfs/icicle: Add USRIO area for userspace IO mappings
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2025-08-15 09:18:34 -03:00
Serg Podtynnyi
2e7f75f6e0 arch/risc-v/rp23xx-riscv: Add rp23xx RISC-V cores support (Hazard3)
Chip name   : rp23xx-rv
Board name  : raspberrypi-pico-2-rv
Arch        : risc-v

Changes from ARM rp23xx impl

- Linker script update
- ASM head start
- Update chip start
- New Hazard3 registers
- Remove rp23xx chip hw spinlocks/testset
- New irq handling (external IRQ interrupt Hazard3)
- New timerisr based on RISC-V std MTIME and alarm arch
- No SMP yet
- Tickless option
- Double size for idle, irq and main stacks
- Board reset via watchdog trigger

Signed-off-by: Serg Podtynnyi <serg@podtynnyi.com>
2025-08-11 08:56:27 +08:00
Eren Terzioglu
1c0e1698cd bugix/risc-v/esp32c6: Fix build error of LP_I2C
Fix build error of LP_I2C for esp32c6

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-08-05 08:00:12 -03:00
Martin Vajnar
150854c6f2 ESP_PCNT: add high and low limit Kconfig options
Signed-off-by: Martin Vajnar <martin.vajnar@gmail.com>
2025-07-22 13:09:02 -03:00
Filipe Cavalcanti
8c932b50fb boards/risc-v: fixes SPI Flash for MCUBoot usage
Adds partitions required for MCUBoot usage and a sample defconfig.

Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
2025-07-22 10:55:08 -03:00
jingfei
db54331479 drivers/fs:Always use register_mtddriver() to register the MTD device (patch2)
This is a supplement to the patch:1936126210a56b6d1b033d6d940669413dd6e1b0

Due to the automatic wrapping of MTD devices during the
open() process, the legacy registration methods
ftl_initialize() and bchdev_register() are no longer
required for MTD device registration for user code.

So we have adjusted the registration method for MTD devices
in nuttx/boards, replacing the previous approach using
ftl_initialize()  with register_mtddriver().
2025-07-21 15:15:30 -03:00
Filipe Cavalcanti
bd18bda0d7 boards/risc-v: add SDMMC defconfigs for ESP32C3|C6|H2
Adds defconfig to support SDMMC over SPI for esp32c3-generic, esp32c6-devkitc,
esp32c6-devkitm and esp32h2-devkit.

Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
2025-07-16 10:24:21 -03:00
Filipe Cavalcanti
6f19c59d26 boards/risc-v: add support for SD Card over SPI on ESP32-C3|C6|H2
Add board support for SD Card over SPI for ESP32C3, ESP32C6 and ESP32H2.

Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
2025-07-16 10:24:21 -03:00
jingfei
d12cf1cb75 drivers/fs:Always use register_mtddriver() to register the MTD device.
We have adjusted the registration method for MTD devices
in nuttx/boards, replacing the previous approach using
ftl_initialize() and bchdev_register() with
register_mtddriver().

When registering MTD devices via register_mtddriver(),
FTL and BCH wrappers will be added during the open() process:

1. Character Device Mode:
   When accessing the MTD device node via the open() interface,
   the device will be automatically converted to a character
   device. Both FTL and BCH wrappers will be implicitly added,
   provided that BCH support is enabled in the configuration.

2. Block Device Mode:
   When accessing the MTD device node via open_blockdriver(),
   the device will be treated as a block device, with only
   the FTL wrapper automatically applied.

Due to the automatic wrapping of MTD devices during the
open() process, the legacy registration methods
ftl_initialize() and bchdev_register() are no longer
required for MTD device registration for user code and should
be used only internally within fs and driver code.

Signed-off-by: jingfei <jingfei@xiaomi.com>
2025-07-16 14:11:41 +08:00