The default bpp is STM32_LTDC_L1_L8, when TM32_FB_CMAP=y,and The default bpp is STM32_LTDC_L1_RGB565 when TM32_FB_CMAP=n. The color-format bpp of stm32f429i is 16, so we should be disable TM32_FB_CMAP, otherwise fb demo will result in an error.
Signed-off-by: jianglianfang <jianglianfang@xiaomi.com>
up_interrupt_context indicates that we self inside interrupt/handler mode,
replaced to private function is_nesting_interrupt to make less confused.
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
The case want to determine if a interrupt with higher priority and the
interrupt preemption occurred, but up_interrupt_context indicates that we
self inside interrupt/handler mode. As we previously did not handle the
ramvector interrupt correctly, after update breaked the case. We should
use a more clear private function is_nesting_interrupt.
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
during migration from legacy pinout some of the FMC pins were ommited because
their names were identical to the new pinout, which didn't cause a compilation error.
This fixes LCD examples.
Also update incomplete stm32f769i-disco FMC support to avoid this kind of bug in the future
Add heap current used to note.
Plot it in segger sysview data plot.
Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
Signed-off-by: Neo Xu <neo.xu1990@gmail.com>
1. Kconfig - Removed USART1 config option from STM32_STM32G47XX. Not necessary to adding LPUART functionality. 2. stm32_lowput.c - Added extra check from STM32G4 board because that is the only with LPUART functionality. 2. stm32_serial.c - Removed unneeded function (stm32_serial_get_lpuart). Fixed up_putc return bug. Added configuration for DMAMAP_LPUART RX and TX for STM32G4XXX only. The G4 is the only in this family with LPUART and uses a DMAMUX unlike the others.
1. Removed 1WIRE LPUART refereences in Kconfig and stm32_uart.h. There is no support for LPUART currently in stm32_1wire.c. 2. Removed references to LPUART under DMA_V2 ifdefs. STM32G4 uses DMA_V1, and I saw that none of the chips DMA_V2 (F20, F4) have LPUARTs. AFAIK the only chip in the stm32 folder that has LPUART peripherals is the STM32G4.
Removed unnecessary brackets and empty lines
Added lpuartnsh (LPUART NuttShell) config to the nucleo-g474re board configurations. nsh uses USART3 by default. lpuartnsh uses nsh as a template, changes the serial console to LPUART1, and adds the DMA configs to enable DMA for the LPUART.
Added support for using the lpuart prescaler register. Without prescaling the apbclock, 9600 baud is not supported on the G474RE. By utilizing the prescaler, when necessary, we can support nearly any baud rate (300 baud to 30M Mbaud). lowputc defaults to a prescaler of 16 for the lpuart so standard baud rates (9600 to 115200) are supported early in the boot process. Later in stm32_serial.c the ideal prescaler and BRR values are determined.
Added ifdef statements for LPUART code sections not compatible with other chips.
Changed LPUART BRR calcuation to use 64-bit integers.
Feedback from nuttx pull request. Added brackets around single line if/else statements. Reordered lpuartnsh defconfig file.
Fix lpuart brr calculation after attempting to break the calculation into 2 lines.
Removed TAB
read content of undefinedinsn address, and compare it with what it is in elf to check if there is a ram bit flip
Signed-off-by: liaoao <liaoao@xiaomi.com>
Summary
MPS-521 support Dual Cortex-M33 and maybe suitable for AMP-like
case which is for AUTO OS, the change
1. add support for single core at msp-521 with nsh bringup
2. testing with ostest
TODO:
Dual core support for flat-build
Dual CORE support for Protected Build
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
Summary
1. add Protected build Support for ARM MPS AN500
2. refine mps Memory layout configure and enable MPU support
Note
1. ostest for an547:nsh
2. ostest for an500:nsh and an500:knsh
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
fix previous problemc
added defconfig for weact-stm32h743:nshusb
board.h
Wrong column position or missing blank line before comment: FIX
hopefully last commit
Since the size of the shadow area will change during the script merging of global variables, it will lead to unpredictable number of links. After fixing, only three links are required.
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
LD: nuttx
arm-none-eabi-ld: /home/ligd/platform/mainline/nuttx/nuttx section `.bss' will not fit in region `ksram'
arm-none-eabi-ld: region `ksram' overflowed by 40 bytes
make[1]: *** [Makefile:212: nuttx] Error 1
make: *** [tools/Unix.mk:538: nuttx] Error 2
Signed-off-by: ligd <liguiding1@xiaomi.com>
arm-none-eabi-ld: /github/workspace/sources/nuttx/nuttx section `.bss' will not fit in region `ksram'
arm-none-eabi-ld: region `ksram' overflowed by 16 bytes
Signed-off-by: zhangshoukui <zhangshoukui@xiaomi.com>
After changing sp, following functions calling will result
in unpredictable behavior in case of jumping
Signed-off-by: wanggang26 <wanggang26@xiaomi.com>
- Edited linker script for shmem to have condition according to cores selected.
- Added new configuration for nsh_cm7_rptun and nsh_cm4_rptun.
- Appended RPTUN bringup code in stm32_bringup.c
Signed-off-by: Nonpawit Ekburanawat <nonpawit.ek@gmail.com>
reason:
1 On different architectures, we can utilize more optimized strategies
to implement up_current_regs/up_set_current_regs.
eg. use interrupt registersor percpu registers.
code size
before
text data bss dec hex filename
262848 49985 63893 376726 5bf96 nuttx
after
text data bss dec hex filename
262844 49985 63893 376722 5bf92 nuttx
size change -4
Configuring NuttX and compile:
$ ./tools/configure.sh -l qemu-armv8a:nsh_smp
$ make
Running with qemu
$ qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic \
-machine virt,virtualization=on,gic-version=3 \
-net none -chardev stdio,id=con,mux=on -serial chardev:con \
-mon chardev=con,mode=readline -kernel ./nuttx
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Basic amg88xx sensor handling (open, close, read, ioctl).
No interrupts supported. I intend to add support for this feature when I
gain more know-how on nuttx/posix.
Make this_cpu is arch independent and up_cpu_index do that.
In AMP mode, up_cpu_index() may return the index of the physical core.
Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
