This PR adds support for the ESWIN EIC7700X RISC-V SoC.
This will be used by the upcoming port of NuttX for PINE64 StarPro64 SBC.
Most of the code was derived from NuttX for SOPHGO SG2000 SoC.
The modified code is explained here:
https://lupyuen.github.io/articles/starpro64#appendix-port-nuttx-to-starpro64
Modified Files in arch/risc-v:
Kconfig: Added ARCH_CHIP_EIC7700X for EIC7700X SoC
New Files in arch/risc-v:
include/eic7700x/chip.h: EIC7700X Definitions
include/eic7700x/irq.h: External Interrupts
src/eic7700x/chip.h: Interrupt Stack Macro
src/eic7700x/eic7700x_allocateheap.c: Kernel Heap
src/eic7700x/eic7700x_head.S: Linux Header and Boot Code
src/eic7700x/eic7700x_irq.c: Configure Interrupts
src/eic7700x/eic7700x_irq_dispatch.c: Dispatch Interrupts
src/eic7700x/eic7700x_memorymap.h: Memory Map
src/eic7700x/eic7700x_mm_init.c, eic7700x_mm_init.h: Memory Mgmt
src/eic7700x/eic7700x_pgalloc.c: Page Allocator
src/eic7700x/eic7700x_start.c: Startup Code
src/eic7700x/eic7700x_timerisr.c: Timer Interrupt
src/eic7700x/hardware/eic7700x_memorymap.h: PLIC and UART Base Address
src/eic7700x/hardware/eic7700x_plic.h: PLIC Register Addresses
src/eic7700x/Kconfig: EIC7700X Config
src/eic7700x/Make.defs: Makefile
Signed-off-by: Lup Yuen Lee <luppy@appkaki.com>
Summary:
This commit removes the riscv_mhartid function and replaces all its
usages with up_cpu_index. The functionality is consolidated into
up_cpu_index which provides a more consistent API for getting the
current CPU/hart ID across different execution modes (machine/supervisor).
Impact:
- Removes riscv_mhartid.S and its references from build systems
- Updates all arch-specific code to use up_cpu_index instead
- Adds more detailed documentation for up_cpu_index behavior
- Changes the implementation of up_cpu_index to use percpu scratch
register in supervisor mode
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Summary:
- Separated CPU index functionality from CPU ID mapping configuration
- Moved CPU ID mapping functions to new riscv_cpuidmap.c file
- Made up_cpu_index() implementation dependent on ARCH_USE_S_MODE
- Updated build system to handle new file organization
Impact:
- Improves code organization by separating concerns between basic CPU index
functionality and advanced CPU ID mapping features
- Makes CPU index functionality available independently of CPU ID mapping
- Reduces conditional compilation complexity in header files
- Better aligns with RISC-V architecture modes (M-mode vs S-mode)
Testing:
GitHub CI and local testing
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This patch refactors the CPU index handling in the RISC-V architecture to be based on the ARCH_RV_CPUID_MAP configuration.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Inline & inline_function both used make confuze, let's modify all inline
in irq.h to inline_function, also clear the always_inline_funcion
declaration.
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
This patch allow public arch level code use them, make it possible to access system register in common code, such as percpu.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
reason:
up_set_current_regs initially had two functions:
1: To mark the entry into an interrupt state.
2: To record the context before an interrupt/exception. If we switch to a new task, we need to store the upcoming context regs by calling up_set_current_regs(regs).
Currently, we record the context in other ways, so the second function is obsolete. Therefore, we need to rename up_set_current_regs to better reflect its actual meaning, which is solely to mark an interrupt.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
reason:
simplify context switch
sys_call0(SYS_switch_context)
sys_call0(SYS_restore_context)
size nuttx
before
text data bss dec hex filename
148021 921 26944 175886 2af0e nuttx
after
text data bss dec hex filename
147995 921 26928 175844 2aee4 nuttx
size reduce -42
Signed-off-by: hujun5 <hujun5@xiaomi.com>
reason:
Replace "inline" with "inline_function" for "up_interrupt_context" to ensure consistency with other arch
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Implement hartid<->cpuid mapping for RISC-V. This is necessary for some
platforms which cannot use 1:1 mapping between logical and physical CPU /
core IDs. One example is MPFS where hart0 cannot be used for NuttX SMP as
it is a less capable "monitor" core (E51) compared to the application
cores hart1...3 (E54).
Why not just use a generic offset then? We also need the physical hart ID
for many things:
- Communication between harts (IPI)
- External interrupt acknowledgment (interrupt claim for specific CPU)
- Communication to SBI
Thus, create procedures that can do this translation:
- The default mapping is still logical=physical.
- Another flavor is to use the existing CONFIG_ARCH_RV_HARTID_BASE config
variable, which is just a simple offset
- The final flavor is to overload hartid<->cpuid on a per chip basis (no
example for this is provided yet)
Some app with same code runs on different cores in AMP mode,
need the physical core on which the function is called.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
This removes 2 reserved system calls and replaces them with an ASM snippet.
The result removes an unnecessary ecall from the process startup logic, as
well as ensures the stacks are FULLY unwound when the user process starts.
The logic is ported from ARM64.
We need to record the parent's integer register context upon exception
entry to a separate non-volatile area. Why?
Because xcp.regs can move due to a context switch within the fork() system
call, be it either via interrupt or a synchronization point.
Fix this by adding a "sregs" area where the saved user context is placed.
The critical section within fork() is also unnecessary.
reason:
1 On different architectures, we can utilize more optimized strategies
to implement up_current_regs/up_set_current_regs.
eg. use interrupt registersor percpu registers.
code size
before
text data bss dec hex filename
262848 49985 63893 376726 5bf96 nuttx
after
text data bss dec hex filename
262844 49985 63893 376722 5bf92 nuttx
size change -4
Configuring NuttX and compile:
$ ./tools/configure.sh -l qemu-armv8a:nsh_smp
$ make
Running with qemu
$ qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic \
-machine virt,virtualization=on,gic-version=3 \
-net none -chardev stdio,id=con,mux=on -serial chardev:con \
-mon chardev=con,mode=readline -kernel ./nuttx
Signed-off-by: hujun5 <hujun5@xiaomi.com>
"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 252: warning #76-D:
argument to macro is empty
SP_DSB();
^
"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 261: warning #76-D:
argument to macro is empty
SP_DMB();
^
"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 252: warning #76-D:
argument to macro is empty
SP_DSB();
^
"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 261: warning #76-D:
argument to macro is empty
SP_DMB();
^
"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 296: warning #76-D:
argument to macro is empty
SP_DSB();
^
Signed-off-by: yanghuatao <yanghuatao@xiaomi.com>
This generalizes the in-kernel syscall approach from KERNEL mode to
all build modes so that to unify in-kernel syscall invocations. As
a result, machine mode ECALL and the supervisor folder are no longer
needed.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
This change implements a driver for the two watchdog timers on the BL808, and enables it as part of the timer config. The driver is based on the GP timer driver.
This commit implements a character driver for the general purpose ADC of the BL808, based on the hardware scanning functionality. The driver supports setting different conversion resolutions and the order of channels to be scanned via menuconfig.
It turns out that the D0 core of the BL808 has an IRQ that represents all interrupt sources for the M0 core. This change uses this IRQ to access these sources, eliminating the need for IPC between M0 and D0.
This change implements a system for allowing the D0 core (which runs NuttX) to receive forwarded interrupts from the M0 core. This makes it possible for drivers that rely on interrupts to work with peripherals attached to the M0 core.
To simplify processing, the existed SBI function code is just
invoking the ecall and return the error value. This omits
potential return value in "a1", which is defined in SBI doc.
Add the "sbiret" struct so it can handle all the return value.
In addition, there are some minor improvement:
1. move the SBI related interface to a separate file to make it clean.
2. add all necessary SBI ecall interface macro until version 2.0.
3. add an utilty function to convert sbi error numner to standard
error number.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
