Most of the peripheral support matches litex vexriscv-smp.
* arch/risc-v/Kconfig: Defer RV32 selection to core as litex board can do RV64.
* arch/risc-v/src/litex/Make.defs
arch/risc-v/src/litex/hardware/litex_clint.h
arch/risc-v/src/litex/hardware/litex_memorymap.h
arch/risc-v/src/litex/hardware/litex_plic.h
arch/risc-v/src/litex/litex_irq.c
arch/risc-v/src/litex/litex_irq_dispatch.c: Add CONFIG_LITEX_CORE_VEXIIRISCV
conditional where vexriscv_smp conditionals are.
* boards/risc-v/litex/arty_a7/configs/nsh-vexii/defconfig: New config.
* boards/risc-v/litex/arty_a7/include/vexii_irq.h: vexiiriscv irq defintion.
* boards/risc-v/litex/arty_a7/include/vexii_memorymap.h: vexiiriscv memory map.
* boards/risc-v/litex/arty_a7/scripts/ld.script: Define __global_pointer for
toolchain happiness matching other RISC-V linker scripts.
(This commit was written with assistance from Claude Code.)
Signed-off-by: Justin Erenkrantz <justin@erenkrantz.com>
- ARCH_CHIP_ESP32C3_LEGACY created
- ARCH_CHIP_ESP32C3_GENERIC is now ARCH_CHIP_ESP32C3
This is part of deprecating esp32c3-devkit as esp32c3-legacy and
using esp32c3-generic (now esp32c3-devkit) instead.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
Since the bl602 do not support the atomic extention, we should compile
it with `-march=rv32imfc`, or it will fail to boot when executing the
`lr.w` instruction.
Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
The Kconfig entry `ESPRESSIF_ESP32[C3|C6|H2]` can be removed as the
already existing `ARCH_CHIP_ESP32[C3_GENERIC|C6|H2`] fulfills its
purpose completely.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
There is no more linking error for MPFS after the flagging is corrected in
drivers/timers/arch_alarm.c
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Add up_perf_ functions for MPFS, which don't rely on alarm/oneshot interface.
Also add optimized up_udelay and up_ndelay functions, which use the MTIMER
directly to measure time; making them accurate and more multithreading friendly.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
This commit disables the esptool's stubs when flashing ESP32-C3
(`CONFIG_ESPRESSIF_ESPTOOLPY_NO_STUB=y`) if the serial/JTAG console
is enabled (`CONFIG_ESPRESSIF_USBSERIAL=y`).
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
This PR adds support for the ESWIN EIC7700X RISC-V SoC.
This will be used by the upcoming port of NuttX for PINE64 StarPro64 SBC.
Most of the code was derived from NuttX for SOPHGO SG2000 SoC.
The modified code is explained here:
https://lupyuen.github.io/articles/starpro64#appendix-port-nuttx-to-starpro64
Modified Files in arch/risc-v:
Kconfig: Added ARCH_CHIP_EIC7700X for EIC7700X SoC
New Files in arch/risc-v:
include/eic7700x/chip.h: EIC7700X Definitions
include/eic7700x/irq.h: External Interrupts
src/eic7700x/chip.h: Interrupt Stack Macro
src/eic7700x/eic7700x_allocateheap.c: Kernel Heap
src/eic7700x/eic7700x_head.S: Linux Header and Boot Code
src/eic7700x/eic7700x_irq.c: Configure Interrupts
src/eic7700x/eic7700x_irq_dispatch.c: Dispatch Interrupts
src/eic7700x/eic7700x_memorymap.h: Memory Map
src/eic7700x/eic7700x_mm_init.c, eic7700x_mm_init.h: Memory Mgmt
src/eic7700x/eic7700x_pgalloc.c: Page Allocator
src/eic7700x/eic7700x_start.c: Startup Code
src/eic7700x/eic7700x_timerisr.c: Timer Interrupt
src/eic7700x/hardware/eic7700x_memorymap.h: PLIC and UART Base Address
src/eic7700x/hardware/eic7700x_plic.h: PLIC Register Addresses
src/eic7700x/Kconfig: EIC7700X Config
src/eic7700x/Make.defs: Makefile
Signed-off-by: Lup Yuen Lee <luppy@appkaki.com>
Following the https://github.com/apache/nuttx/pull/14741, add the
`ARCH_HAVE_RAMFUNCS` config to ESP32-C6 and ESP32-H2 to suppress
the RWX memory region warning.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
This patch refactors the CPU index handling in the RISC-V architecture to be based on the ARCH_RV_CPUID_MAP configuration.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
In https://github.com/apache/nuttx/pull/13044,
LIBC_ARCH_ATOMIC was finally removed.
Howerver, the following chips still have the config.
- ARCH_CHIP_ESP32S3
- ARCH_CHIP_ESP32C3_GENERIC
- ARCH_CHIP_ESP32H2
This commit fixes the issue.
`ARCH_HAVE_RAMFUNCS` has no actual effect on the ESP32-C3,
but ESP32-C3 has RAM functions, so select it to mark that is OK,
and then we can also suppress the RWX memory region warning.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
The number of exception for risc-v is 16 (0 ~ 15)
for the machine ISA version 1.12 or earlier, the number of exception is 20
(0 ~ 19) from the ISA version 1.13. And maybe changed in the future.
Using a dedicated option to control the exception number to allow the earlier
version chip with customized exception number (e.g. 16 ~ 19 used) to define
the exception reason string correctly.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Provides two implementations:
- CSR_CYCLE: Cores which implement hardware performance monitoring.
- CSR_TIME: Uses the machine time registers.
Using the up_perf_xx bindings directory is more efficient than performing a nanosecond conversion on every gettime event.
This patch unifies the extended context save/restore for RISC-V,
allowing the customized context save/restore to be used, for example,
the extended context in rv32m1.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This PR configures the BL808 MMU to cache the the User Text, Data and Heap. We enable the T-Head MMU Flags for Shareable, Bufferable and Cacheable, as explained in the previous PR: https://github.com/apache/nuttx/pull/13199
This PR fixes the Slow Memory Access for NuttX Apps on Ox64 BL808 SBC: https://github.com/apache/nuttx/issues/12696. With this fix, Ox64 NuttX CoreMark jumps from 19 to 1,104. (Close to Buildroot Linux CoreMark)
Modified Files:
`arch/risc-v/Kconfig`: Enabled `ARCH_MMU_EXT_THEAD` for BL808 SoC.
This PR configures the T-Head MMU to cache the the User Text, Data and Heap. We enable the MMU Flags for Shareable, Bufferable and Cacheable, as explained in this article: https://lupyuen.github.io/articles/plic3#appendix-mmu-caching-for-t-head-c906
This PR fixes the Slow Memory Access for NuttX Apps on BL808 and SG2000 SoCs: https://github.com/apache/nuttx/issues/12696. With this fix, SG2000 NuttX CoreMark jumps from 21 to 2,423. (Close to SG2000 Debian CoreMark)
We introduce a Kconfig Option: `ARCH_MMU_EXT_THEAD` ("System Type > Enable T-Head MMU extension support"). Enabling this Kconfig Option will configure the T-Head MMU to cache the User Text, Data and Heap.
This PR enables the MMU cache for only SG2000 SoC (Milk-V Duo S SBC). The next PR will apply the same settings to BL808 SoC (Pine64 Ox64 SBC).
Modified Files:
`arch/risc-v/Kconfig`: Added Kconfig Option `ARCH_MMU_EXT_THEAD` that will configure the T-Head MMU. Enabled `ARCH_MMU_EXT_THEAD` for SG2000 SoC.
`arch/risc-v/src/common/riscv_mmu.h`: Set the T-Head MMU Flags (Shareable, Bufferable and Cacheable) for User Text, Data and Heap, if `ARCH_MMU_EXT_THEAD` is enabled
`arch/risc-v/src/common/riscv_addrenv.c`: Extended the MMU Flags from 32 bits to 64 bits, to accommodate the T-Head MMU Flags
`arch/risc-v/src/common/riscv_exception.c`: Extended the MMU Flags from 32 bits to 64 bit, to accommodate the T-Head MMU Flags. This code is enabled only for MMU Paging (`CONFIG_PAGING`).
Summary:
1.Modify the conditions for entering different include header files
2.Added pre-definition for _Atomic _Bool when it is missing
3.Added nuttx for stdatomic implementation. When toolchain does not support atomic, use lib/stdatomic to implement it
Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
Some multicore RV chips (mpfs, jh7110 etc) have hart clusters
and globally numbered mhartids. Clusters with single hart or
SMP support can be managed by one NuttX instance. Currently
NuttX expects to use cluster-local ids.
This allows us to get local ids by offsetting mhartids with a
base value.
Note that there are chips (e.g. k230) that use cluster-local
ids directly, so this is not needed for them.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
This adds NuttSBI support for rv-virt device so that to enable CI
checks for NuttSBI later. It allows using `-bios nuttx` option to
run NuttX with QEMU v6.2 w/o OpenSBI.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
This PR adds support for the SOPHGO SG2000 SoC, based on T-Head C906 64-bit RISC-V Core. This will be used by the upcoming port of NuttX for Milk-V Duo S SBC.
Most of the code was derived from NuttX for Ox64 BL808. The source files are explained in the articles here: https://github.com/lupyuen/nuttx-sg2000
Modified Files in arch/risc-v:
`Kconfig`: Added ARCH_CHIP_SG2000 for SG2000 SoC
New Files in arch/risc-v:
`include/sg2000/chip.h`: SG2000 Definitions
`include/sg2000/irq.h`: External Interrupts
`src/sg2000/chip.h`: Interrupt Stack Macro
`src/sg2000/sg2000_allocateheap.c`: Kernel Heap
`src/sg2000/sg2000_head.S`: Linux Header and Boot Code
`src/sg2000/sg2000_irq.c`: Configure Interrupts
`src/sg2000/sg2000_irq_dispatch.c`: Dispatch Interrupts
`src/sg2000/sg2000_memorymap.h`: Memory Map
`src/sg2000/sg2000_mm_init.c`, `sg2000_mm_init.h`: Memory Mgmt
`src/sg2000/sg2000_pgalloc.c`: Page Allocator
`src/sg2000/sg2000_start.c`: Startup Code
`src/sg2000/sg2000_timerisr.c`: Timer Interrupt
`src/sg2000/hardware/sg2000_memorymap.h`: PLIC and UART Base Address
`src/sg2000/hardware/sg2000_plic.h`: PLIC Register Addresses
`src/sg2000/Kconfig`: SG2000 Config
`src/sg2000/Make.defs`: Makefile
There is no need to use kernel build for S-mode all the time. As cpu
scratch is supported for non kernel mode build, it is possible to use
flat build for S-mode.
Add flat build support for risc-v S mode.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
This adds support of rv64ilp32 toolchain available from Github repo
`ruyisdk/riscv-gnu-toolchain-rv64ilp32`. With this 32-bit nuttx can
be generated for RV64 devices.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
SSTC extension allows nuttx to implement S-mode timer directly,
which is useful for starting at S-mode.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
In some special chipsets, multiple CPUs may be bundled in one hardware
thread cluster, which results in hartid and cpuindex not being exactly
the same. The new option will decouple Scratch-based Per-CPU storage
with S-Mode to distinguish the real cpu index.
Signed-off-by: chao an <anchao@lixiang.com>
LLVM supports (to various degrees) a number of experimental extensions.
All experimental extensions have experimental- as a prefix. There is
explicitly no compatibility promised between versions of the toolchain,
and regular users are strongly advised not to make use of experimental
extensions before they reach ratification.
Fix compile error:
riscv64-unknown-elf-clang: error: invalid arch name 'rv64gcv_zfh_zvfh', requires '-menable-experimental-extensions' for experimental extension 'zvfh'
Signed-off-by: chao an <anchao@lixiang.com>
K230 chip has two T-Head C908 RiscV cores, previously we run NuttX
on either little or big cores. This patch runs NuttX on both cores
with OpenAMP support via the RPTUN driver.
New additions:
- in arch/risc-v/src/k230
- k230_rptun.c K230 RPTUN driver
- k230_rptun.h K230 RPTUN driver header file
- in baords/risc-v/k230/canmv230
- configs/master Build config for master node
- configs/remote Build config for remote node
- scripts/ld-rptun.script Build script for RPTUN
Major changes:
- arch/risc-v/Kconfig Select NUTTSBI_LATE_INIT upon NUTTSBI
- in arch/risc-v/include
- k230/irq.h Add UART3 IRQ defs
- in arch/risc-v/src/k230
- Kconfig Add RPTUN related config items
- Make.defs Add k230-rptun.c to sources
- hardware/k230_memorymap.h Add K230 device and CSR defs
- k230_hart.c Add hart ctrl for RPTUN
- k230_hart.h Add hart ctrl for RPTUN
- k230_mm_init.c Add Svpmbt to support RPTUN
- k230_start.c Revised to support RPMsg UART
- in boards/risc-v/k230/canmv230
- scripts/Make.defs Add RPTUN script selection
- src/canmv_init.c Add RPTUN and RPMsg_UART initialization
- in Documentation/platforms/risc-v/k230/boards/canmv230
- index.rst Add AMP usage information.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
