Commit graph

8 commits

Author SHA1 Message Date
wangmingrong1
c6a528ef11 spinlock: fix stxr instruction status register requirement
error: unpredictable STXR instruction, status is also a source
   99 |     "stxr     %w0, %1, [%2] \n"
      |      ^
<inline asm>:5:10: note: instantiated into assembly here
    5 | stxr     w10, x10, [x9]
Using w0 to pass the result can cause the "status register is also a source" problem, resulting in unpredictable behavior.

Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2025-06-26 20:31:19 +08:00
lipengfei28
82cf59bff5 arch/arm64: use UP_DSB, UP_DMB, UP_ISB as barrier standard API
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2025-01-20 20:13:07 +08:00
lipengfei28
2d1af01d44 mem barrier: use UP_DMP UP_DSP as barriers standard API
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2025-01-20 20:13:07 +08:00
Alin Jerpelea
879d38d511 arch/arm64: migrate to SPDX identifier
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2024-12-02 22:43:23 +08:00
Petro Karashchenko
d499ac9d58 nuttx: fix multiple 'FAR', 'CODE' and style issues
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2024-08-25 19:22:15 +08:00
hujun5
4cb419866f arch: inline up_testset in arm arm64 riscv xtensa
test:
Configuring NuttX and compile:
$ ./tools/configure.sh -l qemu-armv8a:nsh_smp
$ make
Running with qemu
$ qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic \
   -machine virt,virtualization=on,gic-version=3 \
   -net none -chardev stdio,id=con,mux=on -serial chardev:con \
   -mon chardev=con,mode=readline -kernel ./nuttx

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-08-21 01:45:10 +08:00
yanghuatao
fecc5091af toolchain/ghs: Fix SP_DSB warnings
"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 252: warning #76-D:
          argument to macro is empty
        SP_DSB();
               ^

"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 261: warning #76-D:
          argument to macro is empty
    SP_DMB();
           ^

"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 252: warning #76-D:
          argument to macro is empty
        SP_DSB();
               ^

"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 261: warning #76-D:
          argument to macro is empty
    SP_DMB();
           ^

"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 296: warning #76-D:
          argument to macro is empty
        SP_DSB();
               ^

Signed-off-by: yanghuatao <yanghuatao@xiaomi.com>
2024-08-11 14:28:12 -03:00
qinwei1
e77b06721b arch: arm64: ARMv8-A support for NuttX
N/A

Summary:

Arm64 support for NuttX, Features supported:

1. Cortex-a53 single core and SMP support: it's can run into nsh shell at
   qemu virt machine.

2. qemu-a53 board configuration support: it's only for evaluate propose

3. FPU support for armv8-a: FPU context switching at NEON/floating-point
  TRAP is supported.

4. psci interface, armv8 cache operation(data cache) and smccc support.

5. fix mass code style issue, thank for @xiaoxiang781216, @hartmannathan @pkarashchenko

Please refer to boards/arm64/qemu/qemu-a53/README.txt for detail

Note:
1. GCC MACOS issue
The GCC 11.2 toolchain for MACOS may get crash while compiling
float operation function, the following link describe the issue
and give analyse at the issue:

https://bugs.linaro.org/show_bug.cgi?id=5825

it's seem GCC give a wrong instruction at certain machine which
without architecture features

the new toolchain is not available still, so just disable the MACOS
cibuild check at present

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2022-07-14 09:35:49 -04:00