1. up_irq_save should not mask fiq if CONFIG_ARCH_HIPRI_INTERRUPT=y
2. up_irq_save should mask fiq if CONFIG_ARCH_TRUSTZONE_SECURE=y
3. up_irq_save should mask irq if CONFIG_ARCH_TRUSTZONE_SECURE=n
4. add up_secure_irq in arm64
5. add ARCH_HAVE_TRUSTZONE support for ARCH_CORTEX_R82
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Gdbstub demo::
The Qemu version must be above 9.2 to support two serial ports.
One window:
./tools/configure.sh qemu-armv8a:gdbstub; make -j25
qemu-system-aarch64 -cpu cortex-a53 -nographic -machine virt,virtualization=on,gic-version=3 -net none -kernel ./nuttx -serial mon:stdio -serial pty
char device redirected to /dev/pts/27 (label serial1)
- Ready to Boot Primary CPU
- Boot from EL2
- Boot from EL1
- Boot to C runtime for OS Initialize
Another window:
gdb-multiarch nuttx -ex "target remot /dev/pts/27"
GNU gdb (Ubuntu 15.0.50.20240403-0ubuntu1) 15.0.50.20240403-git
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License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.
Type "show copying" and "show warranty" for details.
This GDB was configured as "x86_64-linux-gnu".
Type "show configuration" for configuration details.
For bug reporting instructions, please see:
<https://www.gnu.org/software/gdb/bugs/>.
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<http://www.gnu.org/software/gdb/documentation/>.
For help, type "help".
Type "apropos word" to search for commands related to "word"...
Reading symbols from nuttx...
Remote debugging using /dev/pts/26
gdb_get_registers (state=0x403e1590) at gdbstub/lib_gdbstub.c:1020
1020 reg = state->running_regs;
(gdb) c
Signed-off-by: hujun5 <hujun5@xiaomi.com>
common/arm64_cache.c:305:38: error: value size does not match register size specified by the constraint and modifier [-Werror,-Wasm-operand-widths]
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
Make sure the registers context size is aligned to 16bytes as required by armv8-a.
This issue has been reported earlier, thus make sense to make sure it won't happen in future.
Signed-off-by: Neo Xu <neo.xu1990@gmail.com>
zynq-mpsoc and zcu111 borad was broken by #15437, because #15437 changes
ARM64_CONTEXT_REGS from 36 to 37, resulting in the stack no longer being
16-byte aligned which appears to violate the ARMv8-A architecture's
requirement for 16-byte stack alignment. this commit changes ARM64_CONTEXT_REGS
to 38 to fix this issues.
The method is the same as the method of saving the current DAIF state of the thread
It will pave the way for the future implementation of hwasan's memory management
Allows each thread to independently control the mte switch function
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
Inline & inline_function both used make confuze, let's modify all inline
in irq.h to inline_function, also clear the always_inline_funcion
declaration.
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
reason:
up_set_current_regs initially had two functions:
1: To mark the entry into an interrupt state.
2: To record the context before an interrupt/exception. If we switch to
a new task, we need to store the upcoming context regs by calling up_set_current_regs(regs).
Currently, we record the context in other ways, so the second function is obsolete. Therefore,
we need to rename up_set_current_regs to better reflect its actual meaning, which is solely to mark an interrupt.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
time/lib_localtime.c: In function 'tz_lock':
time/lib_localtime.c:396:7: error: 'tpidr_el1' undeclared (first use in this function)
396 | if (up_interrupt_context() || (sched_idletask() && OSINIT_IDLELOOP()))
| ^~~~~~~~~~~~~~~~~~~~
Signed-off-by: ligd <liguiding1@xiaomi.com>
when we build mbedtls in vela with ghs compiler, the mbedtls need to
access __ARM_ARCH and __ARM_FEATURE_DSP, and to construct the inline asm
code based on these two macros.
With ghs compiler, these two macros are not defined, and will be
evaluated as 0 by default, and thus will using to wrong inline asm code,
in order to handle this issue, we need to add conversion between the ghs
and gcc with __ARM_ARCH, __ARM_FEATURE_DSP
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
If the core id needs to be included in the hardware register
calculation, up_cpu_index() should be used instead of this_cpu().
Signed-off-by: chao an <anchao@lixiang.com>
Some app with same code runs on different cores in AMP mode,
need the physical core on which the function is called.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
Since FPU is now always saved into the current process stack location
upon exception entry, there is no need to keep fpu_regs (or saved_fpu_regs)
in the TCB.
reason:
when a context switch occurs, up_switch_context is executed.
In order to reduce the time taken for context switching,
we inline the up_switch_context function.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
reason:
1 On different architectures, we can utilize more optimized strategies
to implement up_current_regs/up_set_current_regs.
eg. use interrupt registersor percpu registers.
code size
before
text data bss dec hex filename
262848 49985 63893 376726 5bf96 nuttx
after
text data bss dec hex filename
262844 49985 63893 376722 5bf92 nuttx
size change -4
Configuring NuttX and compile:
$ ./tools/configure.sh -l qemu-armv8a:nsh_smp
$ make
Running with qemu
$ qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic \
-machine virt,virtualization=on,gic-version=3 \
-net none -chardev stdio,id=con,mux=on -serial chardev:con \
-mon chardev=con,mode=readline -kernel ./nuttx
Signed-off-by: hujun5 <hujun5@xiaomi.com>
There is a tiny possibility that when a process is started a trap is
taken which causes a context switch. This moves the kernel stack
unexpectedly and the task start logic no longer works.
Fix this by recording the initial context location, and use that to
trampoline into the user process with interrupts disabled. This ensures
the context stays intact AND the kernel stack is fully unwound before
the user process starts.
This is the initial version for kernel mode build on the arm64 platform.
It works much in the same way as the risc-v implementation so any
highlights can be read from there.
Features that have been tested working:
- Creating address environments
- Loading init (nsh) from elf file
- Booting to nsh
- Starting other processes from nsh
- ostest runs to completion
Features that are not tested / do not work:
- SHM / shared memory support
- Kernel memory mapping (MM_KMAP)
- fork/vfork
An example qemu target is provided as a separate patch:
tools/configure.sh qemu-armv8a:knsh
reduce the time consumed by function call
test:
We can use qemu for testing.
compiling
make distclean -j20; ./tools/configure.sh -l qemu-armv8a:nsh_smp ;make -j20
running
qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic -machine virt,virtualization=on,gic-version=3 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Current `CONFIG_PAGING` refers to an experimental implementation
to enable embedded MCUs with some limited RAM space to execute
large programs from some non-random access media.
On-demand paging should be implemented for the kernel mode with
address environment implementation enabled.
To compile arm64 NuttX, use the following command:
./tools/configure.sh -l qemu-armv8a:nsh_fiq
To run，use the following command
qemu-system-aarch64 -cpu cortex-a53 -nographic -machine virt,virtualization=on,gic-version=3 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx
Signed-off-by: hujun5 <hujun5@xiaomi.com>
N/A
Summary:
Arm64 support for NuttX, Features supported:
1. Cortex-a53 single core and SMP support: it's can run into nsh shell at
qemu virt machine.
2. qemu-a53 board configuration support: it's only for evaluate propose
3. FPU support for armv8-a: FPU context switching at NEON/floating-point
TRAP is supported.
4. psci interface, armv8 cache operation(data cache) and smccc support.
5. fix mass code style issue, thank for @xiaoxiang781216, @hartmannathan @pkarashchenko
Please refer to boards/arm64/qemu/qemu-a53/README.txt for detail
Note:
1. GCC MACOS issue
The GCC 11.2 toolchain for MACOS may get crash while compiling
float operation function, the following link describe the issue
and give analyse at the issue:
https://bugs.linaro.org/show_bug.cgi?id=5825
it's seem GCC give a wrong instruction at certain machine which
without architecture features
the new toolchain is not available still, so just disable the MACOS
cibuild check at present
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
