1. up_irq_save should not mask fiq if CONFIG_ARCH_HIPRI_INTERRUPT=y
2. up_irq_save should mask fiq if CONFIG_ARCH_TRUSTZONE_SECURE=y
3. up_irq_save should mask irq if CONFIG_ARCH_TRUSTZONE_SECURE=n
4. add up_secure_irq in arm64
5. add ARCH_HAVE_TRUSTZONE support for ARCH_CORTEX_R82
Signed-off-by: hujun5 <hujun5@xiaomi.com>
This initial implementation sets up support for the EMMC interfaces on
the BCM2711. Only EMMC2 is tested since it is the interface of interest
(connects to uSD card). MMCSD communication is functional and the boot
partition of the SD card can be mounted and interacted with.
Insertion/removal interrupts do not fire after initial boot, and
sdstress fails with any byte size larger than 1023. 32GB card works
perfectly, while 64GB card exhibits strange behaviour when interacting
with VFAT filesystem.
Signed-off-by: Matteo Golin <matteo.golin@gmail.com>
1. Add hw_tags.c, which will call arm64_mte to implement tagging of memory blocks by operating registers
2. It has been able to run normally on the default NX memory allocator, excluding mempool and tlsf
3. On more complex configurations, memory tests such as memstress can run normally without system crashes
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
This PR adds support for the Allwinner A527 Arm64 SoC.
This will be used by the upcoming port of NuttX for
PINE64 Yuzuki Avaota-A1 SBC.
Most of the code was derived from NuttX for
QEMU Arm64 Kernel Build qemu-armv8a:knsh.
The modified code is explained here:
https://lupyuen.github.io/articles/avaota#appendix-port-nuttx-to-avaota-a1
Modified Files in arch/arm64:
Kconfig: Added ARCH_CHIP_SUNXI for Allwinner 64-bit SoCs.
Added ARCH_CHIP_SUNXI_A527 for A527 SoC.
New Files in arch/arm64:
include/a527/chip.h: A527 Definitions
include/a527/irq.h: External Interrupts
src/a527/chip.h: Memory Map
src/a527/a527_boot.c, a527_boot.h: Startup Code
src/a527/a527_initialize.c: Power Management
src/a527/a527_lowputc.S: UART Output
src/a527/a527_serial.c: Serial Driver
src/a527/a527_textheap.c: Text Heap
src/a527/a527_timer.c: A527 Timer
src/a527/Kconfig: A527 Config
src/a527/Make.defs, CMakeLists.txt: Makefiles
Signed-off-by: Lup Yuen Lee <luppy@appkaki.com>
Includes a Mini-UART NSH console for the 4B, tested on the 4GB RAM
model. Part of an I2C driver which can only read, boiler-plate for a SPI
driver, and a GPIO driver with limited pins. Some tools are present for
automatically fetching the boot files and creating the `config.txt` file
based on selected Kconfig options.
Enforcing the default 48-bit VA for everyone also implies a 4 page table
translation system. However, if less than 40 bits are needed, a full
translation table level can be dropped, making the translations faster.
Thus, make this into a configurable option, instead of enforcing the same
address widht for everyone.
Search and replace ARCH_BOOT_EL3 with more generic
ARCH_ARM64_EXCEPTION_LEVEL that holds the EL level
in an integer variable.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
This provides means to run NuttX completely in EL3. This may
be useful with NuttX based bootloaders that are executed from
OCRAM. Instead of SPL/U-boot combo, NuttX may replace SPL
completely.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Adds support for NXP i.MX9-series System-on-Module chips.
- Support for i.MX93 is added
- CPU is Cortex A55 / ARMv8.2A
- The chip also contains a Cortex M33, but no support is provided
- Supported drivers include lpuart only for now
To compile arm64 NuttX, use the following command:
./tools/configure.sh -l qemu-armv8a:nsh_fiq
To run，use the following command
qemu-system-aarch64 -cpu cortex-a53 -nographic -machine virt,virtualization=on,gic-version=3 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Summary
Add ARM PCSI (Power State Coordination Interface) Support
for qemu. With the interface, Poweroff/PowerReset can be support
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Summary:
Adding virtual evaluate platform GoldFish. Which is based on
Android Goldfish Emulator, it's a ARM virt board but Android enhance
it with more featue
The patch set goldfish as a chip
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Pinephone Pro port just nsh
Status:
booting till GICD / IRQ issue
style cleanups
start to fix style checks
revert offset
whitespaces
revert a64 bringup file
prob last cleanup
more cleanups
remove dts
move changes from a64 hardware specific folders to rk3399
undo common changes (except head.s)
revert gitignore
missing irq.h and rk3399_serial.c need to finish cleaning them up
WIP
add source for load address
make debug print hex again add board include
Pinephone Pro port just nsh
Status:
booting till GICD / IRQ issue
style cleanups
start to fix style checks
revert offset
whitespaces
revert a64 bringup file
prob last cleanup
more cleanups
remove dts
move changes from a64 hardware specific folders to rk3399
undo common changes (except head.s)
revert gitignore
missing irq.h and rk3399_serial.c need to finish cleaning them up
WIP
add source for load address
remove ccache, add board memory map
remove board reset
Summary
Qemu virt board can choice CPU core with boot parameter
and we need to add Konfig option for choice
the change do this
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Sumary
add hostfs support for arm64, it's a copy
from arm32.
Note:
it's not support for opendir and readdir, command
like ls will not work.
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Summary:
Keeping this option out of depend on any common serial.
Using the option, need to implement xxx_lowputc.S/c.
You can also logging the booting message through rewriting
fake arm64_lowputc with other debug method (eg semihosting,
ARM debug channel etc).
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Summary:
To reduce the count of FPU context switching will result at a
performance improve with system. it need to balance between
the using of FPU and counts of FPU trap
the PR submit a base method to see performance counts for
the FPU with NuttX procfs
Please read README.txt at chapter of FPU Support and Performance
for more information
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
On a GICv2 implementation, setting GICC_CTLR.EOImode to 1 separates
the priority drop and interrupt deactivation operations.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
