Commit graph

38 commits

Author SHA1 Message Date
hujun5
c55954d56c barrier: add UP_RMB UP_WMB
This commit added linux-style UP_RMB() and UP_WMB().

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2025-12-22 10:22:06 -03:00
lipengfei28
6949c82310 arch/arm:use UP_DSB, UP_DMB, UP_ISB as barrier standard API
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2025-01-20 20:13:07 +08:00
buxiasen
89455bc9a1 arch: up_getusrsp change to inline and implement in irq.h
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2025-01-06 23:03:05 +08:00
buxiasen
7a0ea108f6 arch/arm-m: add api getpsp, for exception direct case
For exception_direct causing unwind to read NULL and breaks thread backtrace.

Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2025-01-06 23:03:05 +08:00
buxiasen
9bdcc4dc4b arch/irq.h: update all inline to inline_function
Inline & inline_function both used make confuze, let's modify all inline
in irq.h to inline_function, also clear the always_inline_funcion
declaration.

Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2025-01-06 23:03:05 +08:00
hujun5
0e1b432dd0 armv7/8m: fix regresion from https://github.com/apache/nuttx/pull/14881
reason:
svc call may trigger hardfault

Background
    The origin of this issue is our desire to eliminate the function of storing
"regs" in g_current_regs and instead utilize (*running_task)->xcp.regs for storage.
The benefits of this approach include faster storage speed and
avoiding multiple accesses to g_current_regs during context switching,
thus ensuring that whether returning from an interrupt or an exception,
we consistently use this_task()->xcp.regs

Issue Encountered
    However, when storing registers, we must ensure that (running_task)->xcp.regs is invalid
so that it can be safely overwritten.
According to the existing logic, the only scenario where (running_task)->xcp.regs
is valid is during restore_context. We must accurately identify this scenario.
Initially, we used the condition (running_task)==NULL for this purpose, but we deemed
this approach unsatisfactory as it did not align well with the actual logic.
(running_task) should not be NULL. Consequently, we adopted other arch-specific methods for judgment,
but due to special logic in some arch, the judgment was not accurate, leading to this issue.

Solution:
    For armv6-m, we haven't found a more suitable solution, so we are sticking with (*running_task)==NULL.
    For armv7-m/armv8-m, by removing support for primask, we can achieve accurate judgment.

    PRIMASK is a design in armv6-m, that's why arm introduce BASEPRI from armv7-m.
It's wrong to provide this option for armv7-m/armv8-m arch.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-09 12:20:13 +08:00
Alin Jerpelea
344968b8c2 arch/arm: migrate to SPDX identifier
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2024-12-06 09:25:23 +08:00
hujun5
610efc8f1a arm: remove up_set_current_regs/up_current_regs
reason:
up_set_current_regs initially had two functions:

1: To mark the entry into an interrupt state.
2: To record the context before an interrupt/exception. If we switch to
   a new task, we need to store the upcoming context regs by calling up_set_current_regs(regs).

Currently, we record the context in other ways, so the second function is obsolete.
Therefore, we need to rename up_set_current_regs to better reflect its actual meaning,
which is solely to mark an interrupt.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-11-26 20:04:54 +08:00
guoshichao
6036a318f4 compiler: add __ARM_ARCH, __ARM_FEATURE_DSP macro definition in ghs
when we build mbedtls in vela with ghs compiler, the mbedtls need to
access __ARM_ARCH and __ARM_FEATURE_DSP, and to construct the inline asm
code based on these two macros.
With ghs compiler, these two macros are not defined, and will be
evaluated as 0 by default, and thus will using to wrong inline asm code,
in order to handle this issue, we need to add conversion between the ghs
and gcc with __ARM_ARCH, __ARM_FEATURE_DSP

Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2024-11-11 22:18:05 +08:00
hujun5
e249dd2672 arch: support customized up_cpu_index() in AMP mode
Some app with same code runs on different cores in AMP mode,
need the physical core on which the function is called.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
2024-10-10 02:38:40 +08:00
ligd
f20ae064b0 armv7/8m: unmask all the IRQ when thread start
NVIC_SYSH_PRIORITY_MIN not the basepri loweest prio
spec says:
basepri 0 - Disables masking by BASEPRI

Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-10 01:01:17 +08:00
hujun5
7eea4223ee arch: move sigdeliver to common code
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-07 13:32:57 +08:00
hujun5
0561b55860 arm: optimize up_interrupt_context used in armv[6/7/8]-m
resson:
using percpu storage for g_current_regs or leveraging interrupt status
registers to determine if code is running within an interrupt context can enhance performance.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-09-19 08:30:09 +08:00
hujun5
6a3a32b185 arch: move up_interrupt_context to arch specific irq.h
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-09-19 08:30:09 +08:00
hujun5
a754c517cc irq: use per-cpu reg to replace g_current_regs
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-09-19 08:30:09 +08:00
hujun5
ea181e2621 arm: armv7-a/r and armv8-r up_cpu_index inline
reason:
inline small code to improve performance

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-09-06 03:44:49 +08:00
pangzhen1
dee4c63adb protected build: userspace threads will unexpectly work in privileged mode after syscall
In protected build mode, the syscall returns without setting correct value for the CONTROL register, which causes the userspace threads working in privileged mode after syscall.

Signed-off-by: pangzhen1 <pangzhen1@xiaomi.com>
2024-08-28 13:44:37 +08:00
yanghuatao
3e171489bd toolchain/ghs: Fix green hills toolchain build Vela link error
[elxr] (error #412) unresolved symbols:
 __builtin_frame_address     from libarch.a(arm_checkstack.o)

Signed-off-by: yanghuatao <yanghuatao@xiaomi.com>
2024-08-11 14:27:02 -03:00
anjiahao
94d449e722 arch:Mark key functions to prohibit instrumentation to prevent recursive calls
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2023-12-11 02:06:51 -08:00
wangming9
f8aaed780a arch/armv8-m: Add CONTROL register to xcptcontext.
To simplify the interrupt handling in protected mode.

Signed-off-by: wangming9 <wangming9@xiaomi.com>
2023-08-07 05:43:13 -07:00
zhangyuan21
3d47505ec7 arch/arm: Add a "cc" flag to instructions that may modify condition flag.
Notify the compiler that the condition flag has changed to prevent the
compiler from optimizing and reordering instructions, which may cause exceptions.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-05-18 17:23:16 +08:00
anjiahao
172d467c26 arch:add faultmask register operation to armv7-m & armv8-m
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2023-01-05 23:17:43 +02:00
Xiang Xiao
e17b678a16 compiler.h: Rename inline_function to always_inline_function
reserve inline_function macro for inline keyword

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-09-07 10:24:04 +02:00
Xiang Xiao
d80c2d7419 arch/arm: Remove all lazy fpu related code
since it is broken and inefficient, and then removed by:
commit dc961baaea
Author: chao.an <anchao@xiaomi.com>
Date:   Thu Apr 14 18:07:14 2022 +0800

    arm/armv7-[a|r]: move fpu save/restore to assembly handler

    Save/Restore FPU registers in C environment is dangerous practive,
    which cannot guarantee the compiler won't generate the assembly code
    with float point registers, especially in interrupt handling

    Signed-off-by: chao.an <anchao@xiaomi.com>

commit 8d66dbc068
Author: chao.an <anchao@xiaomi.com>
Date:   Thu Apr 7 13:48:04 2022 +0800

    arm/armv[7|8]-m: skip the fpu save/restore if stack frame is integer-only

    Signed-off-by: chao.an <anchao@xiaomi.com>

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-19 11:09:36 +03:00
Xiang Xiao
7c5b2e3305 arch/arm: Remove FAR and CODE from common/ and arm*/ folder
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-19 00:23:59 +03:00
chao.an
29005bd79f board/arch_fpu*: move arch_[get|cmp]fpu to common arch
rename the arch api:
arch_getfpu  -> up_saveusercontext
arch_cmpfpu  -> up_cmpfpu

Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-18 22:22:16 +08:00
chao.an
7b9978883c arch/arm: optimize context switch speed
The current context save implementation saves registers of each task
to xcp context, which is unnecessary because most of the arm registers are
already saved in the task stack, this commit replace the xcp context with
stack context to improve context switching performance and reduce the tcb
space occupation of tcb instance.

Signed-off-by: chao.an <anchao@xiaomi.com>
2022-03-15 23:03:51 +09:00
Xiang Xiao
0c7517e579 arch: Remove the duplicated syscall.h in each arch
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-27 22:54:13 +08:00
Xiang Xiao
25213c42a5 arch/arm: Remove the empty spinlock.h file
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-25 09:18:53 +09:00
Petro Karashchenko
8d3bf05fd2 include: fix double include pre-processor guards
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-16 11:11:14 -03:00
chao.an
0a8d951837 arch/arm: correct the frame pointer register declare
In AArch32, the frame pointer is stored in register R11 for ARM code or register R7 for Thumb code.
In AArch64, the frame pointer is stored in register X29.

Signed-off-by: chao.an <anchao@xiaomi.com>
2021-08-19 01:26:07 -07:00
Xiang Xiao
7e0db977cc arch/arm: Add CONTROL register bit field definition
and replace all hardcode value

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-08-07 09:20:10 -03:00
Alin Jerpelea
c39339a7a8 arch: arm: include: nxstyle fixes
nxstyle fixes to pass CI

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-03-22 19:28:38 -07:00
Gustavo Henrique Nihei
330eff36d7 sourcefiles: Fix relative path in file header 2021-03-09 23:18:28 +08:00
qiaowei
cddd64fd30 armv8-m: Add stack overflow by stack pointer limit register
Signed-off-by: qiaowei <qiaowei@xiaomi.com>
Change-Id: I0f0ae0fb8edb8e1690b3c5e3e8b3189d51a318b0
2020-05-18 07:21:05 -06:00
Xiang Xiao
7ffafa3654 Remove executable bit from source code
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-05-13 06:32:13 -06:00
Gregory Nutt
6766aa0ed5 Mea Culpa. Fix nxstyle problems from PR879
In a fit of confusion, I accidentally committed PR 879 before it passed its nxstyle check (it did pass all of its build tests, but not the style check).  It was really my intention to merge PR878, but I screwed that up and merged 879 instead.

This PR makes amends by passing all of the .c and .h files modified by PR879 through nxstyle and correcting all reported style problems.
2020-04-26 11:56:15 -03:00
qiaowei
2376d8a266 Porting arch/armv8-m support
1. Add dsp extension; float point based on hardware and software.
2. Delete folder "iar"
3. Add tool chain for cortex-M23 and cortex-M35p

Signed-off-by: qiaowei <qiaowei@xiaomi.com>
Change-Id: I5bfc78abb025adb0ad4fae37e2b444915f477fe7
2020-04-26 07:43:37 -06:00