ligd
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bb281eedfa
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cache: add up_get_xcache_linesize() support
Signed-off-by: ligd <liguiding1@xiaomi.com>
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2023-03-20 17:17:22 +08:00 |
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zhuyanlin
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1b08f607be
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arm/xtensa:cache: flush/clean dcache all if size large than cache size
For performance, if size large than cache size, use xxx_all instead
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
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2022-01-27 15:15:28 +08:00 |
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zhuyanlin
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1b3005accf
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arch:cache_invalidate: fix unalign cacheline invalidate
Only invalidate may corrupt data in unalign start and end.
Use writeback and invalidate instead.
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
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2021-11-24 22:48:13 -06:00 |
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zhuyanlin
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cf1a04d0a2
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xtensa:cache: add lock & unlock feature
Since some xtensa cores cache support lock & unlock feature.
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
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2021-10-22 13:31:32 -03:00 |
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zhuyanlin
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8e6fbe700e
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xtensa:dcache_clean: use DCACHE_LINZESIZE instead of DCACHE_SIZE
Clean_dcache use DCACHE_LINZESIZE instead of DCACHE_SIZE in addr loop
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
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2021-09-13 14:38:57 +08:00 |
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zhuyanlin
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26b4bb3075
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xtensa:cache: fix typo error
use addr instead of add
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2021-09-08 11:19:02 +02:00 |
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zhuyanlin
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7b5c39a9d3
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arch:xtensa: add xtensa_cache code support
Add xtensa_cache code support
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2021-09-07 13:33:31 +08:00 |
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