After `CONFIG_STACK_USAGE` enabled, no "*.su" file was generated, tools/showstack.sh output nothing.
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
On rt10xx chips the MPU didn't got reset, which is needed for use
with bootloaders. Furthermore the TCM sizes where fixed now we use
kconfig symbol to set the size respectively. Also we mark ITCM as
RO/RO so we can't change data we executed from.
The up_saveusercontext function leverages USER_SAVE macro,
which is ordinarily used as a first half of the context switch.
This macro is therefore unsuitable to be used standalone,
it pops return address from the stack and does not return.
This patch adds missing instructions to do what would otherwise
be done by the second half of the context switch.
Tested by compiling and verifying the disassembly - the function
no longer falls through to the next function in the program memory,
push/pop instructions are balanced and stack contents preserved
Signed-off-by: Kerogit <kr.git@kerogit.eu>
This enables the use of the cryptographic accelerator within
the ESP32. The support algorithms are: SHA1, SHA256, SHA384
and SHA512.
Signed-off-by: Vlad Pruteanu <pruteanuvlad1611@yahoo.com>
This implements an interrupt-based SPI driver for the BCM2711 SPI
interfaces (excluding auxiliary SPI interfaces). Only tested on SPI0
since proprietary firmware does not initialize any other SPI interfaces,
and doing so will require reverse engineering.
Fix case for CAN character driver in simulator when CANFD is disabled
and ch_edl field is not present in CAN header.
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
Interrupts should be disabled during the access to the user signature
area in internal flash memory, otherwise the system might be halted.
This applies also for read operation as this is performed with a
special flash commands on a special part of memory.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Fix some misspelled field names.
These field names seem to be used only in private contexts.
Thus, the probability of external code accessing these fields is very
low.
In the rare case of external usage, compile time errors will easily
direct users to the new field name.
Properly select physical bank for block erase based on block number.
Previously, it would configure flash erase bank select based on the logical bank. If banks were swapped, and user application
tried to erase the first block of logical bank 2 (expecting to erase starting at 0x08100000), it would actually erase starting
at 0x0800000. This is fixed in this commit.
Signed-off-by: Tyler Bennett <tbennett@2g-eng.com>
After a mailing list suggestion, the indirection that enabled
ARCH_TOOLCHAIN_GCC only when user requested it is removed.
The indirection was a safety measure for chips and boards with linker
scripts that (possibly) do not handle keeping for example .vectors
section even if the linker considers it unreferenced.
Instead, all existing configurations now disable
CONFIG_DEBUG_OPT_UNUSED_SECTIONS to prevent the linker from removing
any code. (Preserving previous behaviour.) This can be removed again
at some point after making sure that corresponding linker script
only removes code that is truly unused.
Signed-off-by: Kerogit <kr.git@kerogit.eu>
- Add ELE command to initialize the ELE RNG context.
- Add ELE command to poll the readiness of the RNG
- Add ELE command to obtain random numbers.
- Replace AHAB_ prefixes with ELE_
- Cleanup header includes
- Added some explanatory comments on .../hardware/imx9_ele.h
Signed-off-by: Theodore Karatapanis <tkaratapanis@census-labs.com>
Even when enabled, the PCNT counter doesn't accumulate into the 32-bit value.
Instead, a value in range [PCNT_LOW_LIMIT, PCNT_HIGH_LIMIT] is always returned.
This is due to interrupt events associated with limit overflows are disabled on the periphery,
therefore the ISR responsible for the accumulation never gets called.
Fixed by enabling the associated interrupt events.
Signed-off-by: michal matias <mich4l.matias@gmail.com>
Add ability to use arv8m systick lowerhalf driver
Fix wrong macro for systick current register in initialize
Signed-off-by: Serg Podtynnyi <serg@podtynnyi.com>
The watchdog auto-monitor sets up during the register phase,
so we should be prepared before calling register.
Signed-off-by: Serg Podtynnyi <serg@podtynnyi.com>
The l1entry replace cause huge time when text/data is big,
Need 16KB per task to hold l1table.
Also critical_section no longer required, as table per-task maintained.
For complex goldfish emulator scarios can speed up:
enter_nsh/application_init_done,
from 23.517300/05:07.067500
to 01.501500/00:06.587300
at least 10 times faster.
As we don't have do x_NPAGES swap out etc.
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
Or will be catch by codespell, when do checkpatch.sh
Also fix the relative comment file changed.
include/nuttx/scsi.h
drivers/syslog/ramlog.c
excluded as we have to modify field name in struct
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
Notice: the up_addrenv_pa_to_va is not correct, it will be complex if we
search all address to lookup all virtual address according to physical
address.
Use up_addrenv_x method as common interface across va & pa
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
BUILD CMD: ./tools/configure.sh -l sama5d3x-ek/nx; make -j`nproc`
chip/sam_memories.c:705:17: note: each undeclared identifier is reported only once for each function it appears in
chip/sam_memories.c:706:27: error: 'CONFIG_SAMA5_DDRCS_PGHEAP_SIZE' undeclared (first use in this function); did you mean 'CONFIG_SAMA5_DDRCS_HEAP_SIZE'?
706 | poolend = poolstart + CONFIG_SAMA5_DDRCS_PGHEAP_SIZE;
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| CONFIG_SAMA5_DDRCS_HEAP_SIZE
make[1]: *** [Makefile:168: sam_memories.o] Error 1
make[1]: Target 'libarch.a' not remade because of errors.
make: *** [tools/LibTargets.mk:170: arch/arm/src/libarch.a] Error 2
make[1]: Target 'libsched.a' not remade because of errors.
make: *** [tools/LibTargets.mk:71: sched/libsched.a] Error 2
make: Target 'all' not remade because of errors.
~/nuttx/tools/testbuild.sh: line 385: ~/nuttx/../nuttx/nuttx.manifest: No such file or directory
Signed-off-by: wangzhi16 <wangzhi16@xiaomi.com>
- Corrected the typo in the comment of the arch/arm/src/arm/arm_cache.S file.
- Standardized the cache terminology, changing "D-cache" and "I-cache" to "Dcache" and "Icache" for consistency with existing code style.
Signed-off-by: EmomaxD <emreleno@gmail.com>
- Added "infor" to .codespellrc ignore-words-list.
This term is used by NXP's ROMAPI naming conventions and is not a typo
in this context.
- This prevents CI/CD codespell checks from failing due to false positives.
Signed-off-by: Theodore Karatapanis <tkaratapanis@census-labs.com>
MMU initialization is redundant for bootloaders(BL2) that load TF‑A(BL31).
TF-A will ignore and overwrite any MMU configuration performed by BL2.
Additionally the MMU comes with a large memory footprint (~50 KB)
which could be precious for such setups.
When the MMU is disabled all the memory is treated as device memory and
all alignment faults generate exceptions (as opposed to normal memory when
MMU is enabled). For that reason we need to add -fno-builtin when compiling
with CONFIG_ARCH_USE_MMU != y to prevent alignment faults.
- Guard MMU initialization with CONFIG_ARCH_USE_MMU
- If CONFIG_ARCH_USE_MMU is not set add -fno-builtin which prevents alignment errors.
- Deliberately didn't try to replace CONFIG_ARCH_HAVE_MMU with CONFIG_ARCH_USE_MMU
occurrences, because this will break a lot of build targets that assume MMU without
guarding the MMU initialization.
Signed-off-by: Theodore Karatapanis <tkaratapanis@census-labs.com>
