In a kernel build vfork() is reached through a system call, so the return
address and stack pointer the architecture's entry point can see for itself
are the kernel's, not the caller's. A child built from those resumes at a
kernel address, which is why x86_64 selected the fork family only for the
flat build.
x86_64_syscall() now publishes the caller's frame in xcp.sregs for the
duration of the stub call, and x86_64_fork() builds the child from it:
x86_64_fork_syscall() when xcp.sregs is non-NULL, so that the child
returns from the very same `syscall' instruction as
the parent, in user mode, on its own stack;
x86_64_fork_direct() otherwise, which is the flat build and any kernel
thread that calls the entry point as a plain
function.
The discriminator is xcp.sregs rather than TCB_FLAG_SYSCALL, which arm64 and
RISC-V use: that flag also defers signal actions, x86_64 has never raised it,
and its kernel-build signal path does not survive being made to -- a
pre-existing problem that does not belong to this work.
Two properties of SYSCALL/SYSRET shape the child's frame. The instruction
leaves the caller's RIP and RFLAGS in RCX and R11 rather than on a stack, so
they are moved into the RIP and RFLAGS slots of the interrupt frame the child
is resumed from; and the hardware never records the caller's CS and SS at all,
SYSRETQ reconstructing them from IA32_STAR, so the child's are filled in with
the user code and data selectors at RPL 3. The frame is therefore not copied
wholesale: the extended state and the general registers are inherited, while
the segment registers and the thread pointer stay as up_initial_state() left
them, the child's stack being a fresh allocation the parent's FS base does not
describe.
x86_64_fork_relocfp() is new and is not optional here. A function returns
with `leave', which feeds the frame pointer into the stack pointer, so
relocating only the RBP the child resumes with gets it exactly one frame:
the next return loads a saved RBP still pointing into the parent's stack.
With that in place ARCH_X86_64 can select ARCH_HAVE_VFORK unconditionally.
Build-verified on qemu-intel64:knsh_romfs and qemu-intel64:ostest. NuttX on
qemu-intel64 requires tsc-deadline and pcid, which TCG does not implement, so
it cannot be run on this host.
Assisted-by: Claude Code:claude-opus-5
Signed-off-by: Marco Casaroli <marco.casaroli@gmail.com>
Signed-off-by: humzak711 <humzak711@gmail.com>
This commit defines the UP_WFE() macro as the 'pause' instruction for
x86_64. This optimization reduces power consumption and prevents
pipeline flushes caused by memory ordering violations during contended
spinlock acqusitions
Rename STACK_ALIGNMENT macro to STACKFRAME_ALIGN throughout the codebase
to provide clearer naming semantics. The new name better reflects the macro's
purpose of frame alignment rather than general stack alignment.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
When an interrupt occurs, the hardware automatically pushes the current RIP/RSP onto the interrupt stack. During the interrupt return, the iretq instruction pops them back. The problem is that the RIP/RSP modified by the signal is stored in the XCP context, whereas iretq operates on the interrupt stack. As a result, the RIP/RSP modified by the signal does not take effect in the iretq instruction, causing the task receiving the signal to fail to jump correctly to the signal handler. This behavior appears as if the signal is lost
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
add acpi procfs function
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
arch/x64:Fix the issue of dereferencing before null check
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
Add support to disable signals actions related struct
Co-authored-by: guoshichao <guoshichao@xiaomi.com>
Signed-off-by: Chengdong Wang <wangchengdong@lixiang.com>
/home/ajh/work/vela_system/nuttx/include/arch/syscall.h:181: Error: operand type mismatch for `movq'
`rax`: Used in 64-bit mode, suitable for storing 64 bits of data.
`eax`: In 64-bit mode, typically used for operating on 32-bit data. When writing to `eax`, the high 32 bits of `rax` are automatically cleared to zero.
`nbr` is an unsigned int, is 32-bit.
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
On newer x86 CPUs, the MSR_IA32_TSC_ADJUST register is utilized to fine-tune the offset of the Time Stamp Counter (TSC). This commit introduces support for MSR_IA32_TSC_ADJUST and enhances the TSC tickless
driver, optimizing its performance.
Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
Add support for stack canaries for x86.
This includes mostly fixes for TLS support that are required for stack canaries
in x86. The FSBASE register must be unique per thread so we have to keep it in
thread registers area.
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
This commit fixed `fb_putc` for early-print.
- Modified fb_putc to return an int instead of void.
- Handled error cases where the character is not found by replacing it with a '.'.
- Ensured cursor position is updated correctly after each character is processed.
- Fixed above 4G framebuffer memory mapping.
Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
This commit introduces support for querying TSC frequency using CPUID 0x40000010. This function can be tested with the following command: `sudo qemu-system-x86_64 -enable-kvm -cpu host,+invtsc,+vmware-cpuid-freq -m 2G -kernel nuttx -nographic -serial mon:stdio -s`
Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
Inline & inline_function both used make confuze, let's modify all inline
in irq.h to inline_function, also clear the always_inline_funcion
declaration.
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
By default in SMP, obtaining this_task requires disabling interrupts, obtaining the current CPU index, accessing a global variable, and re-enabling interrupts. Storing this_task in percpu makes retrieval faster.
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
We save interrupted TCB state on tcb->xcp.regs not interrupt stack now
which allows us to remove x86_64_savestate() from up_switch_context()
and other places.
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Some app with same code runs on different cores in AMP mode,
need the physical core on which the function is called.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
GOTPCRELX reloc available only for CONFIG_ARCH_ADDRENV=y
when CONFIG_ARCH_ADDRENV is not set, CONFIG_ARCH_TEXT_VBASE is not specified
so we can't relocate
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
These are changes to make HPET work with ACRN hypervisor:
- FSB interrupt delivery (which works like PCI MSI)
- 32-bit mode support
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
