Aksal/nuttx
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22675 commits

Author SHA1 Message Date
liwenxiang1
4c19e75ff5 libs/x86_64:Add the setjmp/longjmp function 
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
 2024-10-09 22:24:03 +08:00
wangmingrong1
47fc3a67f7 sim/kconfig: delete non-existent dependencie 
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
 2024-10-09 21:27:47 +08:00
yinshengkai
034af29aab arch: adjust gcov configuration name 
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
 2024-10-09 21:27:47 +08:00
liwenxiang1
8fe6c0ee8e arch/x86_64: Map the new page table with read-write permissions 
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
 2024-10-09 20:51:58 +08:00
Filipe Cavalcanti
42b7097cc2 xtensa/esp32s3: fix missing peripheral initialization for watchdog timer 2024-10-09 20:49:48 +08:00
liwenxiang1
eb411101c5 arch/x86_64:Configure arch delay using CONFIG_ALARM_ARCH 
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
 2024-10-09 20:49:19 +08:00
ligd
784937a03c arm64: fix backtrace failed 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2024-10-09 20:47:43 +08:00
Bowen Wang
f172f222be arm64_checkstack: fix crash, optimize the stack color, sync with arm 
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2024-10-09 20:47:43 +08:00
wangming9
3054b1ad51 arch/arm64: Fixed arm64_cache_get_info obtaining cache. 
Summary:
Select icache or dcache by setting register csselr_el1.

Signed-off-by: wangming9 <wangming9@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2024-10-09 20:47:43 +08:00
wangming9
cb62c783a9 arch/arm64: Add the interface for icache and dcache. 
Summary:
Add up_get_icache_size、up_invalidate_icache、up_get_dcache_size

Signed-off-by: wangming9 <wangming9@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2024-10-09 20:47:43 +08:00
wangmingrong1
0866010101 arm64/makefile: No longer using hwasan pile insertion 
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
 2024-10-09 18:15:13 +08:00
ligd
26dc3b297a arm64: exclude mpu from sanitize for SMP mode 
CPU0 boot -> mm_init() -> sannitize on -> boot other CPUs
CPU1 boot -> mpu_init -> error

Signed-off-by: ligd <liguiding1@xiaomi.com>
 2024-10-09 18:15:13 +08:00
ligd
e9617583bc arm64-r/mpu: add TBI setting to r82 when use SW_TAG 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2024-10-09 18:15:13 +08:00
yinshengkai
73d9a1b4a2 sim: disable sim uart output processing 
Using the host serial port to send data in sim will convert \r to \r\n

Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
 2024-10-09 18:13:46 +08:00
raiden00pl
e419d2c392 arch/arm/Kconfig: fix copy-paste error 
ARCH_CHIP_CSK6 has nothing to do with ST chips:
fix option string and move below ST related options
 2024-10-09 18:11:20 +08:00
liwenxiang1
8b86f5de60 arch/x86_64: add support for thread_local 
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
 2024-10-09 17:58:01 +08:00
liwenxiang1
5e15fff58a arch/x68_64: properly align ap boot stack for vector operations 
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
 2024-10-09 17:40:37 +08:00
liwenxiang1
b4c4cbc28b arch/x86_64: Resolve weak symbol compilation relocation errors 
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
 2024-10-09 17:39:42 +08:00
lipengfei28
56495bc9ce The gicv2m spinlock init status should unlocked 
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
 2024-10-09 15:07:37 +08:00
hujun5
17ca45e8a3 sim: fix sim smp boot regression 
This commit fixes the regression from https://github.com/apache/nuttx/pull/13716

Signed-off-by: hujun5 <hujun5@xiaomi.com>
 2024-10-09 12:33:21 +08:00
Xiang Xiao
b068e2357a circbuf: Move from mm/circbuf to libs/libc/misc 
so that it can be used by userspace program.

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Signed-off-by: Neo Xu <neo.xu1990@gmail.com>
 2024-10-09 08:41:49 +08:00
chenzhijia
a443a37390 drivers/coresight:ETM4 setup 
Signed-off-by: chenzhijia <chenzhijia@xiaomi.com>
 2024-10-09 08:37:48 +08:00
ligd
6dc08ee681 pci: fix compile failed, fdt_get_reg_base() need 3 args 
goldfish: fix compile failed, fdt_get_irq_by_path() need 4 args

Signed-off-by: ligd <liguiding1@xiaomi.com>
 2024-10-09 02:18:49 +08:00
liwenxiang1
cd03ec3266 arch/x86_64:Add check stack function 
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
 2024-10-09 01:53:09 +08:00
liwenxiang1
afe1cc59b6 arch/x86_64: Add vfork support 
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
 2024-10-09 01:41:35 +08:00
anjiahao
9ed93c6b1e unify MODULE & ELF flag to Toolchain.defs 
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
 2024-10-08 19:56:33 +08:00
Ville Juven
e5aef873a2 riscv_internal.h: Remove riscv_sbi.h from the file 
riscv_internal.h is used literally everywhere, while the SBI definitions
are needed only by whomever needs the services.

Having the SBI definitions:
a) Copied from OpenSBI (why has this been done? even the names are same)
b) Presented publicly to 99% of risc-v modules

creates a build error when building with OpenSBI, due to duplicate
definitions of the SBI service identifiers:

In file included from /nuttx/arch/risc-v/src/common/riscv_internal.h:40,
                 from /nuttx/arch/risc-v/src/chip/chip.h:32,
                 from board/mpfs_domain.c:30:
/nuttx/arch/risc-v/src/common/riscv_sbi.h:36: error: "SBI_EXT_BASE" redefined [-Werror]
   36 | #define SBI_EXT_BASE            0x00000010

and so forth...

Fix this by removing riscv_sbi.h i.e. not exposing the ABI publicly.
 2024-10-08 19:55:53 +08:00
yinshengkai
f26ae83900 arch/irq: add the up_getusrpc macro to get the PC of the interrupted thread in the interrupt 
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2024-10-08 19:55:28 +08:00
hujun5
99b364c880 x86_64: fix regression 
This commit fixes the regression from https://github.com/apache/nuttx/pull/13768

Signed-off-by: hujun5 <hujun5@xiaomi.com>
 2024-10-08 15:27:57 +08:00
buxiasen
a6b12eb29c goldfinsh: fix timer compile issue 
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
 2024-10-08 15:27:33 +08:00
ligd
e7094ec40a goldfish: use goldfish timer 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2024-10-08 15:27:33 +08:00
buxiasen
0b3859521a arch: fix the sched parameter update when exiting 
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
 2024-10-08 13:53:06 +08:00
xuxingliang
33a8760a14 arch/sim: fix uart could lose log 
Need to loop to write untill all data written or error happened

Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
 2024-10-08 08:57:28 +08:00
Xiang Xiao
904bb7a6ea arch/sim: dataheap should disable exec permission 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2024-10-08 08:57:28 +08:00
yinshengkai
bdcc325e1f sim/gcov: Fix conflicts between fprofile-orderate and __asan_default_options 
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
 2024-10-08 08:57:28 +08:00
yinshengkai
acca2430a9 Revert "arch/sim: suppress libasan checks" 
This reverts commit 53ddc3ef7f

Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2024-10-08 08:57:28 +08:00
ligd
a3568af105 sim: fix context-switch when do wdog callback() 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2024-10-08 08:57:28 +08:00
ligd
ba3a55b445 cache: do cache_invalidate_all before enable dcache 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2024-10-08 08:15:41 +08:00
raiden00pl
c1c5d8d611 arch/arm/stm32{|f7}/socketcan: fix debugassert for extid frames 
fix debugassert for extid frames, we have to remove
CAN_EFF_FLAG bit from the expression
 2024-10-08 08:14:07 +08:00
hujun5
31a3cea64a arch: rename xxxx_pause.c to xxxx_smpcall.c 
Signed-off-by: hujun5 <hujun5@xiaomi.com>
 2024-10-08 08:13:22 +08:00
hujun5
d8cb7759b6 arch: remove up_cpu_pause up_cpu_resume up_cpu_paused up_cpu_pausereq 
reason:
  To remove the "sync pause" and decouple the critical section from the dependency on enabling interrupts,
  after that we need to further implement "schedlock + spinlock".
changelist
  1 Modify the implementation of critical sections to no longer involve enabling interrupts or handling synchronous pause events.
  2 GIC_SMP_CPUCALL attach to pause handler to remove arch interface up_cpu_paused_restore up_cpu_paused_save
  3 Completely remove up_cpu_pause, up_cpu_resume, up_cpu_paused, and up_cpu_pausereq
  4 change up_cpu_pause_async to up_send_cpu_sgi

Signed-off-by: hujun5 <hujun5@xiaomi.com>
 2024-10-08 08:13:22 +08:00
hujun5
fc22fb8f53 xtensa: Replace the implementation of up_cpu_pause 
Signed-off-by: hujun5 <hujun5@xiaomi.com>
 2024-10-08 08:13:22 +08:00
ligd
b3727f67be esp32: fix esp32 wifi bug caused scan failed 
tools/configure.sh esp32c3-generic:wifi
wapi scan wlan0
has no return result after couple times

rootcause:
mq_timedsend() return failed because the time valid check error.
the ts_nsec is bigger than 1000000000.
esp_update_time() hasn't consider of the ns > 1s after the adding
calculation

Signed-off-by: ligd <liguiding1@xiaomi.com>
 2024-10-07 20:21:45 +08:00
SPRESENSE
9bfc426321 arch: cxd56xx: Add SD card 4-bit capability 
The mmcsd driver has been updated to require SDIO_CAPS_4BIT to be
explicitly specified for SD card 4-bit support.
 2024-10-07 17:35:19 +08:00
xuxingliang
18d5ae20f5 drivers/segger: add heap data plot 
Add heap current used to note.
Plot it in segger sysview data plot.

Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
Signed-off-by: Neo Xu <neo.xu1990@gmail.com>
 2024-10-07 17:34:59 +08:00
xuxingliang
eac6a8597f sched/note: add note when mm add new region 
Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
Signed-off-by: Neo Xu <neo.xu1990@gmail.com>
 2024-10-07 17:34:59 +08:00
xuxingliang
0663ac1483 sched/note: specify note event for heap instrumentation 
1. Add NOTE_HEAP_ prefix for heap note event.
2. Use note type as heap instrumentation parameter.

Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
Signed-off-by: Neo Xu <neo.xu1990@gmail.com>
 2024-10-07 17:34:59 +08:00
yinshengkai
79eab8783f note: add memory tracing event support 
Record all memory allocation and release, save to ram, used to analyze memory allocation rate and memory usage
Its absolute value is not trustworthy because the memory will be allocated in thread A and released in thread B

 netinit-5   [0]   0.105984392: tracing_mark_write: C|5|Heap Usage|96|free: heap: 0x606000000020 size:24, address: 0x603000000370
 netinit-5   [0]   0.105996874: tracing_mark_write: C|5|Heap Usage|24|free: heap: 0x606000000020 size:72, address: 0x6070000008e0
nsh_main-4   [0]   3.825169408: tracing_mark_write: C|4|Heap Usage|2177665|free: heap: 0x606000000020 size:424, address: 0x614000000840
nsh_main-4   [0]   3.825228525: tracing_mark_write: C|4|Heap Usage|14977|free: heap: 0x606000000020 size:2162688, address: 0x7f80a639f800
nsh_main-4   [0]   3.825298789: tracing_mark_write: C|4|Heap Usage|15189|malloc: heap: 0x606000000020 size:20, address: 0x6030000003a0

Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
Signed-off-by: Neo Xu <neo.xu1990@gmail.com>
 2024-10-07 17:34:59 +08:00
lijianjun
9762ddee6e add mm_uninitialize empty implementation for sim 
Signed-off-by: lijianjun <lijianjun@xiaomi.com>
Signed-off-by: Neo Xu <neo.xu1990@gmail.com>
 2024-10-07 17:34:59 +08:00
buxiasen
b444bf2e6a goldfish: fix sched api update missed godlfish_cpuboot 
add cmake support

Signed-off-by: buxiasen <buxiasen@xiaomi.com>
 2024-10-07 17:33:14 +08:00