This revises qemu-armv7a:nsh sample config with the following changes:
- reduced memory size so that `-m 1024` is optional
- enables graceful shutdown from within NuttX
- enables more cases in `ostest`.
Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
Summary:
- Simplified `Make.defs` by including `Toolchain.defs` from the x86 common directory
- Removed redundant toolchain and flag definitions, consolidating them into a single shared file
Impact:
- Reduces code duplication and improves maintainability by centralizing toolchain configurations
- No functional changes - the build process remains the same, but the configuration is now more modular and reusable
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Summary:
- Added LLVM target definitions (`LLVM_ARCH`, `LLVM_CPU`, `LLVM_ABI`) to `arch/x86_64/src/cmake/Toolchain.cmake` and `arch/x86_64/src/common/Toolchain.defs`
- These definitions are necessary for compatibility with LLVM-based toolchains and ensure proper target architecture, CPU, and ABI settings
Impact:
- Enables support for LLVM-based toolchains when building for x86_64 architecture
- No functional changes for existing GNU-based toolchains
- Improves maintainability by centralizing LLVM-specific configurations in the toolchain files
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Summary:
- Added LLVM target definitions (`LLVM_ARCHTYPE`, `LLVM_CPUTYPE`, `LLVM_ABITYPE`) to the x86 toolchain configuration file
- These definitions are necessary for compatibility with LLVM-based toolchains
Impact:
- Enables support for LLVM toolchains when building for x86 targets
- No functional changes for existing GCC-based toolchains
- Improves cross-compilation flexibility by supporting additional toolchain options
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This stops exported LDELFFLAGS from referring to kernel folder
linkscripts because kernel folder might not be present in such
app building use cases.
Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
This adds LDMODULEFLAGS export so that kernel module can build
for kernel mode NuttX via `make import` approach.
Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
Summary:
- Added LLVM_ARCHTYPE, LLVM_CPUTYPE, and LLVM_ABITYPE to the exported build configuration in both `Export.mk` and `mkexport.sh`
- These flags are now included in the generated `makeinfo.sh`, `Make.defs`, and `target.cmake` files during the export process
Impact:
- Enables LLVM-specific build configurations to be properly exported and used in kernel builds
- Improves compatibility with LLVM-based toolchains by ensuring necessary architecture, CPU, and ABI information is available during the build process
- No functional changes for non-LLVM builds, as these flags are only used when LLVM toolchains are specified
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Summary:
- Moved the export of `ZIG` and `ZIGFLAGS` from `tools/Unix.mk` to `tools/Export.mk`
- Simplified the `export` target in `tools/Unix.mk` by removing redundant `ZIG` and `ZIGFLAGS` variables
Impact:
- No functional changes - the `ZIG` and `ZIGFLAGS` variables are still exported correctly
- Improves code maintainability by centralizing environment variable exports in `Export.mk`
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
config-testing-heap is changed to conofig-testing-heap, so the citest tools need to change.
Signed-off-by: tengshuangshuang <tengshuangshuang@xiaomi.com>
after below change merge to kernel, spin_lock() will turn off preemption by default,
but this change is not applicable to all scenarios. The locations in the kernel that
use spin_lock() extensively only require short critical sections and do not trigger
scheduling, which leads to serious performance degradation of NuttX in AMP mode.
In this PR, I try to expose similar problems and hope that each subsystem will carefully check the code coverage
https://github.com/apache/nuttx/pull/14578
|commit b69111d16a
|Author: hujun5 <hujun5@xiaomi.com>
|Date: Thu Jan 23 16:14:18 2025 +0800
|
| spinlock: add sched_lock to spin_lock_irqsave
|
| reason:
| We aim to replace big locks with smaller ones. So we will use spin_lock_irqsave extensively to
| replace enter_critical_section in the subsequent process. We imitate the implementation of Linux
| by adding sched_lock to spin_lock_irqsave in order to address scenarios where sem_post occurs
| within spin_lock_irqsave, which can lead to spinlock failures and deadlocks.
|
| Signed-off-by: hujun5 <hujun5@xiaomi.com>
Signed-off-by: chao an <anchao.archer@bytedance.com>
Coredump doens't need CONFIG_ELF to be enabled, but need elf.h to include correct elf32.h or elf64.h.
Select LIBC_ARCH_ELF in COREDUMP to allow LIBC_ARCH_ELF_64BIT to be
defined correctly.
Signed-off-by: Neo Xu <neo.xu1990@gmail.com>
Firstly call arm_coredump_add_region in up_initialize to add nvic region, then call
coredump_set_memory_region to add board mem region, at this moment, an overlap occurs.
Signed-off-by: wanggang26 <wanggang26@xiaomi.com>
Add a custom note for NuttX information including magic and coredump
file data size, so when system reboots, we can check if the block device
contains valid coredump file, and save it to file system.
Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
ADC peripheral can be configured also for PWM trigger, so the ifdef
should depend only on CONFIG_SAMV7_AFEC_SWTRIG. Also handle the
situation when ANIOC_TRIGGER is called and the peripheral is not
configured for SW trigger (but the other one may be, so config option
is set).
Trigger values saved to the private structure are also changed to
enums for better code clarity.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
reason:
In x86_64, tcb->xcp.regs is always valid, and we obtain the location
where the context is saved through irq_xcp_regs every time an interrupt occurs.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
reason:
We aim to replace big locks with smaller ones. So we will use spin_lock_irqsave extensively to
replace enter_critical_section in the subsequent process. We imitate the implementation of Linux
by adding sched_lock to spin_lock_irqsave in order to address scenarios where sem_post occurs
within spin_lock_irqsave, which can lead to spinlock failures and deadlocks.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
reason:
1 Accelerated the implementation of sched_lock, remove enter_critical_section in sched_lock and
only enter_critical_section when task scheduling is required.
2 we add sched_lock_wo_note/sched_unlock_wo_note and it does not perform instrumentation logic
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Under apps/testing folder, the macro of CONFIG_TESTING_MM is changed to CONFIG_TESTING_HEAP.
So we need to update the defconfig containing CONFIG_TESTING_HEAP in the nuttx/boards folder.
Signed-off-by: tengshuangshuang <tengshuangshuang@xiaomi.com>
UART RAM will have probabilistic bubble time during continuous transmission.
Update the offset after sending to avoid this problem.
Signed-off-by: chao an <anchao.archer@bytedance.com>
add sim_rpmsg_port_uart.c to verify the rpmsg port uart wrapper layer,
The physical transport layer could be:
1. SIM_RAM_UART(current)
2. SIM_UART(through "socat" virtual "/dev/pts/*", "socat" could monitor the bus data)
Signed-off-by: chao an <anchao.archer@bytedance.com>
This forces the bch layer to read the sector from the physical device
instead of using the cached values. It is necessary to call when the
device is updated from the different source than bch, for example
erased by the MTD ioctl command.
It also has to invalidate readahead buffer from FTL if option
CONFIG_DRVR_READAHEAD is set.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
On branch master
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modified: ../../boards/arm/stm32/nucleo-l152re/configs/nsh/defconfig
no changes added to commit (use "git add" and/or "git commit -a")
This removes the need to call nxsched_self upon exception return. Later
with a bit of added logic, it is possible to use tp in kernel to store and
read the current tcb.
Note: setting tp in riscv_restorecontext is too late for this, as
this_task() points to the (next) ready-to-run task, thus tp should be
updated when the rtr list is updated (via up_update_task, which does not
exist for risc-v yet)
