48-pin 1MB F412. CE was the only 48-pin part listed, so boards using
STM32F412CGU6 had to select a 512KB chip. Feature counts are identical
to CE, so it shares the block.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Jacob Dahl <dahl.jakejacob@gmail.com>
100-pin 1MB F412 (LQFP/UFBGA). Without this, boards using
STM32F412VGH6 have to select the 48-pin 512KB CE.
STM32_NGPIO is 113 rather than the real 81 I/Os because
STM32_NGPIO_PORTS is (N+15)>>4 and 81 yields six ports A-F, so
PH0/PH1 could not be configured. 113 matches ZG and gives A-H.
CE/ZG chip.h counts and the family HAVE_* list are corrected in
the same change: CE has no FSMC, the die has TIM6/7/9-14 and
SPI4/5, ZG USART is 4, I2S is 5. FSMC is only bonded on 100/144-pin,
so HAVE_FSMC is selected on VG/ZG and not on CE.
Signed-off-by: Jacob Dahl <dahl.jakejacob@gmail.com>
STM32_NGPIO_PORTS is (N+15)>>4. 81 (the real pin count) yields six
ports A-F, so PH0/PH1 cannot be configured. 113 matches the F40x
100-pin entries and gives A-H.
Signed-off-by: Jacob Dahl <dahl.jakejacob@gmail.com>
BREAKING CHANGE:
Part of splitting the legacy stm32 super-directory; relocates
the stm32f4 sources, headers and boards into arch/arm/src/stm32f4,
arch/arm/include/stm32f4 and boards/arm/stm32f4.
Signed-off-by: raiden00pl <raiden00@railab.me>
