Gregory Nutt
1c394bc278
Rename arch_nshinitialize() to board_app_initialize()
2015-03-31 10:21:31 -06:00
Gregory Nutt
103a17d4f1
Rename arch_nshinitialize() to board_app_initialize()
2015-03-31 10:21:31 -06:00
Gregory Nutt
9c0441e2da
Rename arch_nshinitialize() to board_app_initialize()
2015-03-31 10:21:31 -06:00
Gregory Nutt
e5fd084af2
SAMV71-XULT: Add option to support connection of the maXTouch Xplained Pro on the 50-pin LCD connector
2015-03-31 09:01:38 -06:00
Gregory Nutt
7b3761f4ea
SAMV71-XULT: Add option to support connection of the maXTouch Xplained Pro on the 50-pin LCD connector
2015-03-31 09:01:38 -06:00
Gregory Nutt
eb21ad0cf2
SAMV71-XULT: Add option to support connection of the maXTouch Xplained Pro on the 50-pin LCD connector
2015-03-31 09:01:38 -06:00
Gregory Nutt
519e00eba7
SAMV71-XULT: Add a configuration for testing the maXTouch Xplained Pro connected to the board
2015-03-30 15:31:53 -06:00
Gregory Nutt
c76373280b
SAMV71-XULT: Add a configuration for testing the maXTouch Xplained Pro connected to the board
2015-03-30 15:31:53 -06:00
Gregory Nutt
9057fe2051
Update README
2015-03-30 07:33:48 -06:00
Gregory Nutt
157c56d081
Update README
2015-03-30 07:33:48 -06:00
Gregory Nutt
0e9f358060
SAMV7 Ethernet: Fix a write-past-end-of-buffer and trash-the-heap problem
2015-03-29 16:45:05 -06:00
Gregory Nutt
8aa133029f
SAMV7 Ethernet: Fix a write-past-end-of-buffer and trash-the-heap problem
2015-03-29 16:45:05 -06:00
Gregory Nutt
805be6fee2
Update ChangeLog
2015-03-29 15:39:08 -06:00
Gregory Nutt
f073092fad
The STM32F4Discovery board doesn't come with a Low speed external oscillator so the default LSE source for the RTC doesn't work.
...
In stm32_rtcc.c the up_rtcinitialize() logic doesn't work with the LSI. The check on RTC_MAGIC on the BK0R register lead to rtc_setup() call that rightfully enables the lsi clock; but the next times, when the rtc is already setup, the rtc_resume() call does NOT start the lsi clock!
The right place to put LSE/LSI initialisation is inside stm32_stdclockconfig() in stm32fxxxxx_rcc.c. Doing this I checked the possible uses of the LSI and the LSE sources: the LSI can be used for RTC and/or the IWDG, while the LSE only for the RTC (and to output the MCO1 pin)..
This change is not verifed for any other platforms.
From Leo Aloe3132
2015-03-29 15:34:48 -06:00
Gregory Nutt
f1c79423e1
The STM32F4Discovery board doesn't come with a Low speed external oscillator so the default LSE source for the RTC doesn't work.
...
In stm32_rtcc.c the up_rtcinitialize() logic doesn't work with the LSI. The check on RTC_MAGIC on the BK0R register lead to rtc_setup() call that rightfully enables the lsi clock; but the next times, when the rtc is already setup, the rtc_resume() call does NOT start the lsi clock!
The right place to put LSE/LSI initialisation is inside stm32_stdclockconfig() in stm32fxxxxx_rcc.c. Doing this I checked the possible uses of the LSI and the LSE sources: the LSI can be used for RTC and/or the IWDG, while the LSE only for the RTC (and to output the MCO1 pin)..
This change is not verifed for any other platforms.
From Leo Aloe3132
2015-03-29 15:34:48 -06:00
Gregory Nutt
593e1243dc
Minor Documentation update
2015-03-29 14:46:52 -06:00
Gregory Nutt
eb304951b4
Minor Documentation update
2015-03-29 14:46:52 -06:00
Gregory Nutt
55a7065f07
Cortex-M7: Add support for enabled the D-Cache in write only mode.
...
SAMV7 Ethernet: I- and D-Cache are now enabled in the netnsh/ configuration. D-Cache is enabled in write-though mode. This mode is necessary because the DMA descriptors are each 8-bytes in size but the D-Cache cache line is 32-bits in size. So it is impossible make coherency for every 8-byte DMA descriptor without write-through.
2015-03-29 14:42:03 -06:00
Gregory Nutt
d3beea967d
Cortex-M7: Add support for enabled the D-Cache in write only mode.
...
SAMV7 Ethernet: I- and D-Cache are now enabled in the netnsh/ configuration. D-Cache is enabled in write-though mode. This mode is necessary because the DMA descriptors are each 8-bytes in size but the D-Cache cache line is 32-bits in size. So it is impossible make coherency for every 8-byte DMA descriptor without write-through.
2015-03-29 14:42:03 -06:00
Gregory Nutt
dab3dbc75b
Cortex-M7: Add support for enabled the D-Cache in write only mode.
...
SAMV7 Ethernet: I- and D-Cache are now enabled in the netnsh/ configuration. D-Cache is enabled in write-though mode. This mode is necessary because the DMA descriptors are each 8-bytes in size but the D-Cache cache line is 32-bits in size. So it is impossible make coherency for every 8-byte DMA descriptor without write-through.
2015-03-29 14:42:03 -06:00
Gregory Nutt
7a636fdb13
SAMV7/Cortex-M7: Add support for write through D-Cache. SAMV7 Ethernet look like it needs this
2015-03-29 13:09:22 -06:00
Gregory Nutt
ae0b0ca3fd
SAMV7/Cortex-M7: Add support for write through D-Cache. SAMV7 Ethernet look like it needs this
2015-03-29 13:09:22 -06:00
Gregory Nutt
4593fe3797
SAMV7/Cortex-M7: Add support for write through D-Cache. SAMV7 Ethernet look like it needs this
2015-03-29 13:09:22 -06:00
Gregory Nutt
9319d6c88b
Update documentation
2015-03-29 07:52:52 -06:00
Gregory Nutt
f67c489756
Update documentation
2015-03-29 07:52:52 -06:00
Gregory Nutt
ef1dda9207
PIC32MZ Ethernet: Add support for LAN4720A and fix IRQ namespace. From Kristopher Tate
2015-03-29 07:18:17 -06:00
Gregory Nutt
c221547be4
PIC32MZ Ethernet: Add support for LAN4720A and fix IRQ namespace. From Kristopher Tate
2015-03-29 07:18:17 -06:00
Gregory Nutt
70dc3d68c5
PIC32MZ: Correct the base address of Ethernet registers. From Kristopher Tate
2015-03-29 07:15:29 -06:00
Gregory Nutt
e8b232fc41
PIC32MZ: Correct the base address of Ethernet registers. From Kristopher Tate
2015-03-29 07:15:29 -06:00
Gregory Nutt
9f70633dac
PIC32MZ Ethernet: Enable PBCLK5 and MII divider for PHY. From Kistopher Tate
2015-03-29 07:14:09 -06:00
Gregory Nutt
8bb8f47d0b
PIC32MZ Ethernet: Enable PBCLK5 and MII divider for PHY. From Kistopher Tate
2015-03-29 07:14:09 -06:00
Gregory Nutt
947d1056ac
PIC32MZ: Rename Ethernet files to proper convention. From Kristopher Tate.
2015-03-29 07:10:13 -06:00
Gregory Nutt
6b3c199d9f
PIC32MZ: Rename Ethernet files to proper convention. From Kristopher Tate.
2015-03-29 07:10:13 -06:00
Gregory Nutt
312ae5713e
PIC32MZ Ethernet: Add support for LAN8740A PHY
2015-03-29 07:05:30 -06:00
Gregory Nutt
d85f3dd530
Minor update to a README
2015-03-29 07:04:39 -06:00
Gregory Nutt
b1dcacebe7
Minor update to a README
2015-03-29 07:04:39 -06:00
Gregory Nutt
9b906daa86
SAMV71-XULT: netnsh configuration is back to -O2
2015-03-28 14:54:30 -06:00
Gregory Nutt
ce34402dac
SAMV71-XULT: netnsh configuration is back to -O2
2015-03-28 14:54:30 -06:00
Gregory Nutt
18b26dc8e6
Clean up pointer handling to make code more readability. This re-introduces the compiler optimization problem but this is the correct thing to do. I will have to drop back from -Os to -O2.
2015-03-28 14:46:35 -06:00
Gregory Nutt
a60fa12e86
Clean up pointer handling to make code more readability. This re-introduces the compiler optimization problem but this is the correct thing to do. I will have to drop back from -Os to -O2.
2015-03-28 14:46:35 -06:00
Gregory Nutt
3a93955fb3
SAMV7 EMAC: Fix alignment issue: RX buffers need to be invalidated. This means the alignment of buffers must be at least to the data cache line size at both ends of the buffer
2015-03-28 13:09:01 -06:00
Gregory Nutt
b15cd1653f
SAMV7 EMAC: Fix alignment issue: RX buffers need to be invalidated. This means the alignment of buffers must be at least to the data cache line size at both ends of the buffer
2015-03-28 13:09:01 -06:00
Gregory Nutt
d2fd139ebc
SAMV7 EMAC: Fix alignment issue: RX buffers need to be invalidated. This means the alignment of buffers must be at least to the data cache line size at both ends of the buffer
2015-03-28 13:09:01 -06:00
Gregory Nutt
bbeca4a91c
SAMV7 EMAC: Sometimes TX is not started when TSTART is set??? Workaround seems to be to set it twice. Restored full optimization. Also CONFIG_NET_NOINTS is set so that interrupt level provessing is avoided
2015-03-28 09:42:45 -06:00
Gregory Nutt
afd737ddcc
SAMV7 EMAC: Sometimes TX is not started when TSTART is set??? Workaround seems to be to set it twice. Restored full optimization. Also CONFIG_NET_NOINTS is set so that interrupt level provessing is avoided
2015-03-28 09:42:45 -06:00
Gregory Nutt
d7dbdfef58
SAMV7 EMAC: Sometimes TX is not started when TSTART is set??? Workaround seems to be to set it twice. Restored full optimization. Also CONFIG_NET_NOINTS is set so that interrupt level provessing is avoided
2015-03-28 09:42:45 -06:00
Gregory Nutt
2108499b4f
SAMV71-XULT: Add a network-enabled NSH configuration
2015-03-27 14:18:13 -06:00
Gregory Nutt
756d19ff28
SAMV71-XULT: Add a network-enabled NSH configuration
2015-03-27 14:18:13 -06:00
Gregory Nutt
750fad37f0
SAMV7 Ethernet: Fix some errors in circular queue handling
2015-03-27 13:04:43 -06:00
Gregory Nutt
e57bb047c8
SAMV7 Ethernet: Fix some errors in circular queue handling
2015-03-27 13:04:43 -06:00
