Gregory Nutt
9e546ff37a
Tiva interrupts: Fix chip-specific interrupt un-definitions
2015-01-12 10:00:42 -06:00
Gregory Nutt
b9dcced1aa
Tiva interrupts: Fix chip-specific interrupt un-definitions
2015-01-12 10:00:42 -06:00
Gregory Nutt
90da8aa71d
Tiva Timers: Add interfaces to read the current timer value
2015-01-12 10:00:41 -06:00
Gregory Nutt
487f9a3be9
Tiva Timers: Add interfaces to read the current timer value
2015-01-12 10:00:41 -06:00
Gregory Nutt
e5a0dcd0f9
USB host drivers: Change all parmeters named class to usbclass to avoid C++ conflicts
2015-01-11 08:05:09 -06:00
Gregory Nutt
31a94816b2
USB host drivers: Change all parmeters named class to usbclass to avoid C++ conflicts
2015-01-11 08:05:09 -06:00
Gregory Nutt
b75c43f6ef
Tiva Timer: Fix a typo
2015-01-10 12:42:39 -06:00
Gregory Nutt
2444605b95
Tiva Timer: Fix a typo
2015-01-10 12:42:39 -06:00
Gregory Nutt
3c06976ba7
Tiva Timer: Implements configuration of the 32-bit RTC timer
2015-01-10 12:41:15 -06:00
Gregory Nutt
d09a9e2741
Tiva Timer: Implements configuration of the 32-bit RTC timer
2015-01-10 12:41:15 -06:00
Gregory Nutt
c0e1dc3b8a
Tiva Timer: Add support for RTC match interrupts
2015-01-10 12:22:37 -06:00
Gregory Nutt
2c6cf27405
Tiva Timer: Add support for RTC match interrupts
2015-01-10 12:22:37 -06:00
Gregory Nutt
a2a5c47d9d
Tive Timer: Add support for ADC trigger generation from one-shot and periodic timers for timeout and match evetns
2015-01-10 10:07:56 -06:00
Gregory Nutt
1ea2f5da1c
Tive Timer: Add support for ADC trigger generation from one-shot and periodic timers for timeout and match evetns
2015-01-10 10:07:56 -06:00
Gregory Nutt
2eeca96330
Tiva Timer: Add support to set the match regiser(s) relative to the timer counter (and prescale) registers. Enable match interrupts. These are one time interruprts: After the match interrupt is dispatched, further match interrupts are disabled
2015-01-10 08:34:39 -06:00
Gregory Nutt
9cead4170b
Tiva Timer: Add support to set the match regiser(s) relative to the timer counter (and prescale) registers. Enable match interrupts. These are one time interruprts: After the match interrupt is dispatched, further match interrupts are disabled
2015-01-10 08:34:39 -06:00
Gregory Nutt
2871677362
Tiva Timer: Add support for input clock prescaler in 16-bit one-shot/periodic modes
2015-01-09 16:49:00 -06:00
Gregory Nutt
fa4a54c5ad
Tiva Timer: Add support for input clock prescaler in 16-bit one-shot/periodic modes
2015-01-09 16:49:00 -06:00
Gregory Nutt
df48abcc47
Tiva Timer: Add logic to acknowledge Tiva Timer interrupts
2015-01-09 15:01:49 -06:00
Gregory Nutt
3544eb2fdf
Tiva Timer: Add logic to acknowledge Tiva Timer interrupts
2015-01-09 15:01:49 -06:00
Gregory Nutt
9ae597c441
Tive System Control: Add logic to configure the alternatie clock source (ALTCLK). Needed by the Tiva timer module
2015-01-09 14:10:31 -06:00
Gregory Nutt
64530008ba
Tive System Control: Add logic to configure the alternatie clock source (ALTCLK). Needed by the Tiva timer module
2015-01-09 14:10:31 -06:00
Gregory Nutt
7384857658
Tiva Timer: Add more interrupt management logic
2015-01-09 13:29:03 -06:00
Gregory Nutt
9531dd1a80
Tiva Timer: Add more interrupt management logic
2015-01-09 13:29:03 -06:00
Gregory Nutt
626d6cdab4
Tiva Timer: Add functions to set match registers; Add logic to select count direction
2015-01-09 12:05:26 -06:00
Gregory Nutt
59555646c5
Tiva Timer: Add functions to set match registers; Add logic to select count direction
2015-01-09 12:05:26 -06:00
Gregory Nutt
8552b2f679
Tiva Timer: Add interfaces to start/stop timers and to set the interval load registers.
2015-01-09 11:07:52 -06:00
Gregory Nutt
c092ecb131
Tiva Timer: Add interfaces to start/stop timers and to set the interval load registers.
2015-01-09 11:07:52 -06:00
Gregory Nutt
d5d3a23ac3
Tiva Timers: Add framework to support tmer interrupts
2015-01-09 10:21:59 -06:00
Gregory Nutt
db556691f3
Tiva Timers: Add framework to support tmer interrupts
2015-01-09 10:21:59 -06:00
Gregory Nutt
1193b4aa55
STM32 SDIO: Don't let architectures select CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE unless they have implemented SDIOWAIT_WRCOMPLETE
2015-01-08 17:47:34 -06:00
Gregory Nutt
f787440a04
STM32 SDIO: Don't let architectures select CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE unless they have implemented SDIOWAIT_WRCOMPLETE
2015-01-08 17:47:34 -06:00
Gregory Nutt
09bd382697
Tiva Timer: Partial support for 16- and 32-bit, oneshot and periodic timer configurations
2015-01-08 13:44:10 -06:00
Gregory Nutt
45e09d9df7
Tiva Timer: Partial support for 16- and 32-bit, oneshot and periodic timer configurations
2015-01-08 13:44:10 -06:00
Gregory Nutt
58818e1afd
Tiva Timer: Add support to select alternate clock source and 32-bit register concatenation mode.
2015-01-08 11:08:54 -06:00
Gregory Nutt
4357af2493
Tiva Timer: Add support to select alternate clock source and 32-bit register concatenation mode.
2015-01-08 11:08:54 -06:00
Gregory Nutt
d3bc0b7223
Tiva Timer: Add register level debug support
2015-01-08 10:14:38 -06:00
Gregory Nutt
6715926fab
Tiva Timer: Add register level debug support
2015-01-08 10:14:38 -06:00
Gregory Nutt
6c612cf967
Tiva Timer: Add basic framework to configure timers. Incomplete on initial commit
2015-01-08 09:47:38 -06:00
Gregory Nutt
737108e066
Tiva Timer: Add basic framework to configure timers. Incomplete on initial commit
2015-01-08 09:47:38 -06:00
Gregory Nutt
92dc58c376
Tiva Timer: SYNC regiser is only available on GPTM0
2015-01-08 08:07:31 -06:00
Gregory Nutt
4224fd0edc
Tiva Timer: SYNC regiser is only available on GPTM0
2015-01-08 08:07:31 -06:00
Gregory Nutt
e55df605a8
Tiva Timer: Update timer register bit definitions for the LM4F
2015-01-08 08:03:47 -06:00
Gregory Nutt
ff02574863
Tiva Timer: Update timer register bit definitions for the LM4F
2015-01-08 08:03:47 -06:00
Gregory Nutt
1ed2956ad5
Tiva Timer: Extend timer register definitions to handle other chips
2015-01-08 07:56:00 -06:00
Gregory Nutt
54bf159bdb
Tiva Timer: Extend timer register definitions to handle other chips
2015-01-08 07:56:00 -06:00
Gregory Nutt
1ace391fcf
MMCSD SDIO: Add support for a new SDWAIT_WRCOMPLETE condition. The previous logic used a busy-wait loop to pool the card R1 start to determine when the card was ready for the next transfer. That busy-wait can be quite long -- hundreds of milliseconds. And alternative is to look the the SD D0 pin which will change state when the card is no longer busy.
...
This logic implements a change the avoids the busy-wait poll by reconfiguring the SD D0 pin as a GPIO interrupt, then waiting for the card to becom ready without taking up CPU cycles.
This change is conditioned on CONFIG_MMCSD_SDIOWATI_WRCOMPLETE and is currenlty only implemented for the STM32 SDIO driver.
From David Sidrane
2015-01-08 06:23:42 -06:00
Gregory Nutt
1842525cc2
MMCSD SDIO: Add support for a new SDWAIT_WRCOMPLETE condition. The previous logic used a busy-wait loop to pool the card R1 start to determine when the card was ready for the next transfer. That busy-wait can be quite long -- hundreds of milliseconds. And alternative is to look the the SD D0 pin which will change state when the card is no longer busy.
...
This logic implements a change the avoids the busy-wait poll by reconfiguring the SD D0 pin as a GPIO interrupt, then waiting for the card to becom ready without taking up CPU cycles.
This change is conditioned on CONFIG_MMCSD_SDIOWATI_WRCOMPLETE and is currenlty only implemented for the STM32 SDIO driver.
From David Sidrane
2015-01-08 06:23:42 -06:00
Gregory Nutt
5c68f0dd34
Tiva Timer: Missed one register bit field definition
2015-01-07 12:03:08 -06:00
Gregory Nutt
1f10c56dd0
Tiva Timer: Missed one register bit field definition
2015-01-07 12:03:08 -06:00
