When the system startup from the PL1 SYS mode, the initialization
of the PL2 HYP register needs to be skipped. Put the Hypervisor
initialization code together and skip it all at once.
Signed-off-by: yukangzhi <yukangzhi@xiaomi.com>
Move stack alignment and kernel stack macros from architecture-specific internal
headers to public include/nuttx/irq.h. Consolidates duplicate definitions across
17 architecture families, reducing code duplication while enabling common code
to access these core alignment utilities without architecture dependencies.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
1.add application link dependencies for all elf
2.add a global custom target to hold proptry in the toolchain file
3.add startup obj target
4.fix cpp lds error with kernel mod link elf lds
usage:
./build.sh qemu-armv7a:knsh --cmake
elf install in ${CMAKE_BINARY_DIR}/bin
Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
New rptun framework need provide the carveout device to provide
the share memmory.
And need add the cpuname feature for rpmsg virtio device to let
rpmsg virtio can know remote cpuname.
Signed-off-by: wangzhi16 <wangzhi16@xiaomi.com>
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
Add two new address environment utility functions in arm_addrenv_pgmap.c:
- up_addrenv_find_page(): Find physical page mapped to user virtual address
from address environment page directory (stub implementation for future use)
- up_addrenv_user_vaddr(): Check if virtual address is in user space by calling
arm_uservaddr(). Enables common code to query user address space boundaries
on ARMv7-A architecture.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Add support to disable signals actions related struct
Co-authored-by: guoshichao <guoshichao@xiaomi.com>
Signed-off-by: Chengdong Wang <wangchengdong@lixiang.com>
Fix: Some STM32 chips don't support GTIM_CCER_CC1NP; use HAVE_GTIM_CCXNP guards to exclude it. Adds/updates #ifdef HAVE_GTIM_CCXNP guards so GTIM_CCER_CC1NP is only included when supported, preventing register writes on chips without it.
Signed-off-by: Alexey Matveev <tippet@yandex.ru>
After addrenv_switch(), the current running task (this_task) may change due to
deferred work execution. Update all architecture interrupt, syscall, and exit
handlers to re-fetch tcb = this_task() after addrenv_switch(). Ensures scheduler
and context operations use the correct TCB, preventing context corruption and
exceptions across SMP and memory-protected builds.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Replace direct labels for CPU startup routines with indirection through global
variables. Export cpu1_start, cpu2_start, cpu3_start as global objects containing
addresses to __cpu1_start, __cpu2_start, __cpu3_start respectively. Use load-then-
branch-exchange (ldr r1, =cpu*_start; ldr r1, [r1]; bxeq r1) instead of direct beq
jumps. Enables flexible control of CPU startup positions and supports future AMP/
dynamic loading scenarios.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Add new CONFIG_NCPUS configuration option to support both SMP and AMP modes.
Replace SMP-specific CONFIG_SMP_NCPUS checks with generic CONFIG_NCPUS in ARM
boot code (ARMv7-A, ARMv7-R, ARMv8-R). CONFIG_NCPUS defaults to SMP_NCPUS when
SMP is enabled, or 1 otherwise, enabling multi-CPU support regardless of SMP mode.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Enable SGI (Software Generated Interrupts) usage in AMP mode for inter-core
communication. Modify arm_cpu_sgi() to use SGI_TGTFILTER_LIST for both SMP and
AMP modes instead of requiring CONFIG_SMP. Add CPU0-only guard checks using
sched_getcpu() to ensure arm_gic0_initialize() executes only once on CPU0 during
initialization in both SMP and AMP configurations.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
We need IFF_IS_RUNNING(dev->d_flags) to be true for ethernet device to
work properly. However, dev->d_flags are not set anywhere in the
Kinetis' ethernet code.
This change updates kinetis_ifup and kinetis_ifdown procedures to call
netdev_carrier_on and netdev_carrier_off to set dev->d_flags.
Signed-off-by: Jiri Vlasak <jvlasak@elektroline.cz>
Modify nuttx_generate_preprocess_target() to inject
$<TARGET_PROPERTY:nuttx_global,NUTTX_CPP_COMPILE_OPTIONS> into the
preprocessing command, ensuring that linker script preprocessing uses
the same C preprocessor flags as the rest of the build (e.g., -D defines,
include paths).
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
when we build with greenhills compiler, if the exception_common function
is put into a separate section: ".text.exception_common", then the
address of exception_common function is an even number, for example "0x16a6c",
in this case, it will trigger the UsageFaults:INVSTATE error.
The reason for this error is that in the GHS compiler, a section declared
through the ".section" directive must specify at least the "a" attribute.
Otherwise, this section will not be linked into the final file, and this
is why the address of exception_common function is invalid.
The following is the official explanation in the GHS compiler documentation:
"The reason for this error is that in the GHS compiler, a section
declared through the .section directive must specify at least the "a"
attribute. Otherwise, this section will not be linked into the final
file. The following is the official explanation in the documentation:
"Sections that are intended be part of the final linked output should
have at least the `a` attribute"
and for GHS compiler, the .text section is recommended specify the
attribute of `ax`.
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
SAMV7_EMAC0_RMII should not depend on ARCH_CHIP_SAM4E as this is
a completely different chip. This is likely a relict from copying
the code base.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
- fix chip/imxrt_clockconfig_ver1.h:23: error: header guard '__ARCH_ARM_SRC_IMXRT_IMXRT_CLOCKCONFIG_VER1_H' followed by '#define' of a different macro [-Werror=header-guard]
Signed-off-by: simbit18 <simbit18@gmail.com>
the -ffunction-sections and -fdata-sections are also supported by
greenhills, and these two compile options can benefit with section
layout optimization, and thus reduce the final image size
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
According to the Greenhills documentation, the "-Wall" option is
deprecated for use. Instead, the "-ghstd=last" option is recommended.
Compared with "-Wall", the "-ghstd=last" option can capture more
warnings and has stricter rules.
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
In Green Hills, if the name of the file to be preprocessed ends with ".ld",
this file must be renamed to ".ld.i". Otherwise, the following error will be reported:
ccarm: Error: -o out/build/cmake_out/mann_dcu_evb_ghs_ap/gnu-elf.ld has wrong suffix for -P option (expect .i)
Currently, based on the documentation and actual operations, only files
ending with "*.ld" can trigger this preprocessing error. There are no such
issues in other cases.
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
The TLS initialization logic needs to be updated to match the modified
linker script section definitions. The previous implementation assumed
that _END_TDATA and _START_TBSS were contiguous, but there may be
padding between these sections for alignment purposes.
This commit updates up_tls_initialize() to explicitly account for the
padding gap between _END_TDATA and _START_TBSS when zeroing the .tbss
section. The size calculation in up_tls_size() is also updated to use
_END_TBSS instead of the previous _END_TXXX definition to match the
current linker script layout.
Changes:
- Calculate padding gap: (_START_TBSS - _END_TDATA)
- Zero .tbss at correct offset accounting for padding
- Update size calculation to use proper section boundaries
Signed-off-by: guoshengyuan1 <guoshengyuan1@xiaomi.com>
Reimplement __aeabi_read_tp using naked function with inline assembly
to strictly follow ARM EABI TLS helper specification.
The ARM EABI specifies that __aeabi_read_tp may only modify r0, and
compilers rely on this guarantee by NOT saving r1-r3 registers when
calling this function. The previous simple C implementation could
potentially clobber these registers through compiler optimizations,
violating the ABI contract and causing subtle bugs.
Changes:
- Add __aeabi_read_tp_core() helper to allow tls_get_info() macro
expansion in C context
- Explicitly preserve r1-r3 registers per EABI requirement
This ensures proper register usage compliance for all calling contexts
while maintaining the ability to use tls_get_info() macro correctly.
Reference: ARM EABI TLS Helper Specification
https://github.com/ARM-software/abi-aa/blob/main/rtabi32/rtabi32.rst#thread-local-storage-new-in-v2-01
Signed-off-by: guoshengyuan1 <guoshengyuan1@xiaomi.com>
Ensure the CMake build explicitly locates and links libstdc++.a
when CONFIG_LIBCXXTOOLCHAIN is enabled. This aligns CMake behavior
with the Make build system and fixes STL/libc header conflicts
observed on xmc4800-relax:nsh.
Signed-off-by: trns1997 <trns1997@gmail.com>
When compiling with O2 optimization, the compiler optimizes the code
in a way that causes irq variable to be corrupted. The getipsr()
function reads IPSR into r0, but the subsequent inline assembly that
sets FPSCR also uses r0 without declaring it as clobbered. This causes
the compiler to reuse r0 for the immediate value (0x40000), overwriting
the IRQ number read from IPSR.
The issue manifests as:
- getipsr() correctly reads IPSR (e.g., 0xf for IRQ 15)
- Compiler optimizes and reuses r0 for ARM_FPSCR_LTPSIZE_NONE (0x40000)
- irq variable gets the wrong value 0x40000 instead of actual IRQ number
- This leads to assertion failures in irq_dispatch due to invalid IRQ
Root cause analysis from disassembly:
mrs r0, IPSR ; Read IPSR to r0
mov.w r0, #262144 ; Compiler overwrites r0 with 0x40000!
vmsr fpscr, r0 ; Set FPSCR
str r0, [sp, #4] ; Store corrupted 0x40000 as irq
...
ldr r0, [sp, #4] ; Load corrupted value
bl irq_dispatch ; Call with wrong IRQ number 0x40000
Fix by adding r0 to the clobber list in the inline assembly, which
forces the compiler to save irq value before using r0 for FPSCR setup.
This issue only occurs at O2 optimization level and affects ARMv8-M
architecture with FPU enabled.
Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
armv8m:use ip save pc
armv7m:use ip save pc, r11 save sp
nsh_main backtrace before:
```
0 nxsem_wait_slow (sem=0x10001e0 <g_uart0port+32>) at semaphore/sem_wait.c:202
1 0x0000882c in nxsem_wait (sem=0x10001e0 <g_uart0port+32>) at semaphore/sem_wait.c:270
2 0x0000e7e2 in uart_read (filep=0x608037d4, buffer=0x60c013eb " h\024\300`", buflen=1)
at serial/serial.c:1203
3 0x0001aad4 in file_readv_compat (filep=0x608037d4, uio=0x60c01344) at vfs/fs_read.c:81
4 0x0001abae in file_readv (filep=0x608037d4, uio=0x60c01344) at vfs/fs_read.c:165
5 0x0001ac2e in nx_readv (fd=0, iov=0x60c01388, iovcnt=1) at vfs/fs_read.c:256
6 0x0001ac84 in readv (fd=0, iov=0x60c01388, iovcnt=1) at vfs/fs_read.c:318
7 0x0001acca in read (fd=0, buf=0x60c013eb, nbytes=1) at vfs/fs_read.c:352
8 0x000100ea in STUB_read (nbr=56, parm1=0, parm2=1623200747, parm3=1) at stubs/STUB_read.c:9
9 0x000014d2 in dispatch_syscall () at armv8-m/arm_svcall.c:82
```
nsh_main backtrace after:
```
0 nxsem_wait_slow (sem=0x10001f0 <g_uart0port+32>) at semaphore/sem_wait.c:202
1 0x000088c0 in nxsem_wait (sem=0x10001f0 <g_uart0port+32>) at semaphore/sem_wait.c:270
2 0x0000e882 in uart_read (filep=0x6080380c, buffer=0x60c013eb " h\024\300`", buflen=1)
at serial/serial.c:1203
3 0x0001ab74 in file_readv_compat (filep=0x6080380c, uio=0x60c01344) at vfs/fs_read.c:81
4 0x0001ac4e in file_readv (filep=0x6080380c, uio=0x60c01344) at vfs/fs_read.c:165
5 0x0001acce in nx_readv (fd=0, iov=0x60c01388, iovcnt=1) at vfs/fs_read.c:256
6 0x0001ad24 in readv (fd=0, iov=0x60c01388, iovcnt=1) at vfs/fs_read.c:318
7 0x0001ad6a in read (fd=0, buf=0x60c013eb, nbytes=1) at vfs/fs_read.c:352
8 0x0001018a in STUB_read (nbr=56, parm1=0, parm2=1623200747, parm3=1) at stubs/STUB_read.c:9
9 0x00001ece in dispatch_syscall () at armv8-m/arm_dispatch_syscall.S:111
10 0x2000a874 in read (parm1=0, parm2=0x60c013eb, parm3=1) at proxies/PROXY_read.c:9
11 0x20001152 in readline_getc (vtbl=0x60c01468) at readline_fd.c:73
12 0x20003994 in readline_common (vtbl=0x60c01468, buf=0x60c017f8 "\n", buflen=80)
at readline_common.c:513
13 0x200012ec in readline_fd (buf=0x60c017f8 "\n", buflen=80, infd=0, outfd=1) at readline_fd.c:236
14 0x200010a8 in nsh_session (pstate=0x60c01540, login=1, argc=1, argv=0x60c00548)
at nsh_session.c:229
15 0x20000eb0 in nsh_consolemain (argc=1, argv=0x60c00548) at nsh_consolemain.c:75
16 0x20000e4c in nsh_main (argc=1, argv=0x60c00548) at nsh_main.c:74
17 0x20000062 in nxtask_startup (entrypt=0x20000e11 <nsh_main>, argc=1, argv=0x60c00548)
at sched/task_startup.c:72
18 0x00009ac4 in nxtask_start () at task/task_start.c:106
19 0x60c00548 in ?? ()
Backtrace stopped: previous frame identical to this frame (corrupt stack?)
```
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
* Explicit registration of ttys0 when no console defined
* Fixes overwriting registration of lpuart1 on ttys1 when no console on ttys0
* Change regstration logic to check for console assignment
* See issue 17116
Signed-off-by: dirksavage88 <dirksavage88@gmail.com>
