Updates E-Fuse driver for ESP32S3, now sharing a common implementation across
Xtensa devices.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
Adds SYS_STARTUP_FN which calls constructors and init functions on
common source code. Requires compatibility changes on linker script.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
.tick_start is better in terms of performance than .start for one shot,
so provide this .tick_start implementation
Signed-off-by: Chengdong Wang <wangchengdong@lixiang.com>
This commit fixes E-Fuse driver to get proper block and bit offset.
Also adds support for virtual and flash E-Fuses.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
On a system with multiple CPU cores, when the system is powered on,
multiple cores may start running simultaneously. In this case, software
is required to handle the startup logic for multi-core synchronization.
One approach is to use global variables.
however, the global variable region may not have been initialized yet.
In such scenarios, we can use a busywait flag to
implement the synchronization strategy.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
On a system with multiple CPU cores, when the system is powered on,
multiple cores may start running simultaneously. In this case, software
is required to handle the startup logic for multi-core synchronization.
One approach is to use global variables.
however, the global variable region may not have been initialized yet.
In such scenarios, we can use a busywait flag to
implement the synchronization strategy.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Some iMXRT chips like iMXRT-1050 has two USB controllers, but until
now only USB1 was supported. This patch modify the driver to support
both USBs.
Signed-off-by: Alan C. Assis <acassis@gmail.com>
Give the user the full control over the USIC FIFO buffer even if USIC channel 0 is disabled.
When USICx_CHAN0 is not an UART but USICx_CHAN1 is, the user can set the desired FIFO buffer offsets in CHAN1 config.
Update board reset with BOOTROM functions calls
- normal reboot
- reboot to bootloader
normal reboot and reboot bootloader now possible from nsh
Port of https://github.com/apache/nuttx/pull/16848
Signed-off-by: Serg Podtynnyi <serg@podtynnyi.com>
Fixes low and inconsistent bandwidth issues.
Adds new configuration options for buffer management.
Moves code around to make the implementation cleaner and easier to debug.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
The following warning occurred if ARCH_CHIP_PIC32CZCA70 option was
selected. The variable is not used in case of PIC32CZ CA70 series.
CC: task/task_getgroup.c chip/sam_emac.c: In function ‘sam_emac_initialize’:
chip/sam_emac.c:4758:12: warning: unused variable ‘regval’ [-Wunused-variable]
4758 | uint32_t regval;
|
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
"tc397" is a chip name which is not appropriate to act as a board name.
the board supported here is actually "a2g-tc397-5v-tft".
The correct definition is : tricore is arch name, tc3xx is arch family
name, tc397 is chip name and the borad name is a2g-tc397-5v-tft
imx9_lpi2c_reset didn't quite work. It tried to toggle scl line as GPIO, but the line was not even muxed properly.
Instead, set the bus to relaxed mode, and drive address 0 to the bus. This toggles the clock, and also generates start and stop sequences on the bus.
"Relaxed mode" is a new feature on the LPI2C block used in imx93.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
This removes the need to have all the DDR/clock configuration related
"LIBERODEFS" flags defined, when not building a standalone/coldboot
configuration
All of this code is unused when not building with CONFIG_MPFS_BOOTLOADER
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Introduce EXT1 wakeup functionality to the ESP32-S3 power management
subsystem. With this feature, the ESP32-S3 can wake up from PM_STANDBY
or PM_SLEEP when one or more RTC GPIOs trigger the EXT1 condition.
Changes include:
- Added EXT1 wakeup configuration and preparation logic in rtc code.
- Integrated EXT1 handling in pmstandby() and pmsleep().
- New board-level Kconfig options under ESP32-S3 DevKit menu:
- CONFIG_PM_EXT1_WAKEUP: enable EXT1 wakeup support
- CONFIG_PM_EXT1_WAKEUP_RTC_GPIO<n>: select RTC GPIOs as wake sources
- CONFIG_PM_EXT1_WAKEUP_TRIGGER_MODE: choose wakeup on HIGH or LOW level
- Fixing Kconfig style
- Fixing comments standard
- Adding PM documentation for esp32s3-devkit
Impact:
- No build impact unless CONFIG_PM_EXT1_WAKEUP is enabled.
- When enabled, ESP32-S3 can wake from low-power states via RTC GPIOs.
- No new public API introduced; controlled via board Kconfig.
Tested on ESP32-S3 DevKit:
- Configured GPIO4 and GPIO5 as EXT1 wake sources.
- Verified wakeup from light sleep and deep sleep on external signals.
- Wakeup reason correctly reported as EXT1.
Signed-off-by: Thiago Finelon <thiago.sfinelon@gmail.com>
- In case of warm reboot, clear active and pending interrupts from GICv3
and also from the CPU interface.
- Fix default IGROUPMODR to the reset value (0)
- Move gic_wait_rwp calls to after modifying ICENABLER
- Improve some comments
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Set the affinity of the task before activating it. There is no parameter
or other interface in "kthread_create" to set the affinity mask,
like in "pthread_create".
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
This arch uses code relocation to SRAM through a XIP unit, so forcing segment
permissions manually in the linker script could create unforeseen issues.
A quick fix is setting the "--no-warn-rwx-segments" linker option just for
for the incriminated stage2 bootloader binary.
Signed-off-by: Niccolò Maggioni <nicco.maggioni+nuttx@gmail.com>
fix nooptimiziation_function definition problem for tricore gnu compiler
arch/tricore:
move tricore_csa2addr and tricore_addr2csa definition from include/arch.h to include/irq.h to fix build error
Version 2.2.0 of the SDK unified some headers under a new path.
Now both the old and the new paths are searched during compilation.
Signed-off-by: Niccolò Maggioni <nicco.maggioni+nuttx@gmail.com>
Prior to this commit, it wasn't possible to load ELF modules from
the external PSRAM. There were two main issues about it: 1) copying
data using the instruction bus was being used instead of the data
bus (this, per si, isn't a problem, but requires special attention
regarding data alignment), and 2) the cache was not being properly
cleaned and flushed to properly access the loaded data using the
instruction bus.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
If both SPI Flash support (`CONFIG_ESP32S3_SPIFLASH`) and PSRAM
(`CONFIG_ESP32S3_SPIRAM`) are enabled, the PSRAM can only be
assigned to the user's heap (`CONFIG_ESP32S3_SPIRAM_USER_HEAP`).
Additionaly, `CONFIG_ESP32S3_SPI_FLASH_SUPPORT_PSRAM_STACK` must be
set because the system will end up allocating tasks' stacks from
the external PSRAM. This has an impact when dealing with SPI flash
operations because the cache must be disabled and the running task
should not rely on any data from the PSRAM. To accomplish that, It
offloads the SPI flash operation to a work queue (which, by
definition, allocates its heap from the kernel heap).
The same (assigning the PSRAM to the user's heap) is valid when the
Wi-Fi is enabled because the lower-half driver requires data being
allocated from the internal memory (which can only be achieved by
allocating from the kernel heap when both the kernel and user heaps
exists).
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Use this command to extract archives.
Not all architectures are modified, only those commands I know
or could be logically deducted from the rest were added.
Signed-off-by: Stepan Pressl <pressl.stepan@gmail.com>
The interrupt handler accesses the device as well as the driver's private
data. Thus, must take the big kernel lock in SMP mode to protect them.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
In SMP mode one CPU can be executing the MMC interrupt while another CPU
disables (e.g. via watchdog timeout). As it is disabled the other CPU
assumes it's safe to start configuring the device after this.
This causes a leak in the driver's private data as well as a mutual
exclusion leak on the device itself.
Fix this by aborting any triggered interrupt by checking whether it's
even enabled.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Update board reset with BOOTROM functions calls
- normal reboot
- reboot to bootloader
normal reboot and reboot bootloader now possible from nsh
Signed-off-by: Serg Podtynnyi <serg@podtynnyi.com>
Currently the irq handler checks many reserved bits, which is
a waste of resources:
1. pending_rx_ep bit 0 is reserved (always 0)
2. pending_rx_ep and pending_tx_ep have only bits 1, 2, 3 and 4
defined, no need to scan MPFS_USB_NENDPOINTS (9) bits as the
rest are reserved
Fix this by checking only the relevant bits.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
As emmcsd driver does not support separate WRCOMPLETE interrupt the
SDIOWAIT_WRCOMPLETE event shall not be waited.
The SDIOWAIT_TRANSFERDONE event indicates that both "transfer done"
and "write complete" events are completed.
mpfs_sendcmd() shall not wait for data lines ready before
sending commands to the card. This prevents mmcsd driver
to poll card busy status prior to next activity after
a write operation.
Add capture source files to the makefile pipeline.
STM32H7_CAP to STM32H7_TIMX_CAP for clarity.
Signed-off-by: Côme VINCENT <44554692+comejv@users.noreply.github.com>
