Align the writing style of arm cmake, and each compiler defines its own find library
function, otherwise use the default
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
The tx int handler will call uart_xmitchars() to make a fake interrupt event,
but this is unsafe after enabling interrupts. This PR will add a critical section
to ensure that the txint process will not be interrupted by the IRQ
Signed-off-by: chao an <anchao.archer@bytedance.com>
GICD_ICFGR requires full 32-bit RMW operations.
Each interrupt uses 2 bits; thus updates must be synchronized
to avoid losing configuration in concurrent environments.
RMW conflict on GICD_ICFGRn (without lock)
CPU0 (set IRQ32 edge) CPU1 (set IRQ33 level)
--------------------- -----------------------
val0 = read(ICFGRn) │ val1 = read(ICFGRn)
│
val0 |= (edge << 4) │
│ val1 &= ~(3 << 6)
│
write(ICFGRn, val0) │
│ write(ICFGRn, val1)
=> IRQ32 config lost OR IRQ33 config lost
(depends on which write finishes last)
Concurrent RMW on ICFGRn causes lost config.
Protect with spinlock to avoid data race.
Since interrupt type configuration is infrequent,
a single global GIC lock is sufficient (no need for
fine-grained locking per ICFGR register).
Signed-off-by: Shen Cao <caoshen3@lixiang.com>
Commit 83a119160 fixed SMP by removing call to uart_xmitchars from inside spinlock.
This only works for SMP, since uart_xmitchars has a lock only in SMP. In a single
core configuration the function can be called in parallel from the interrupt
handler and from the imx9_txint.
Fix this by filling the uart buffers already before enabling the
interrupt, this way it is not possible to get the function called in parallel
for the same device.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
This product does not have MTE. MTE is only available for Arch or higher extensions of armv8-5+memory tags
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
1. Add hw_tags.c, which will call arm64_mte to implement tagging of memory blocks by operating registers
2. It has been able to run normally on the default NX memory allocator, excluding mempool and tlsf
3. On more complex configurations, memory tests such as memstress can run normally without system crashes
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
1. When the Clang compiler turns on "-fsanitize=kernel-address", inlining, global variables, and stack detection are enabled by default and must be turned off manually.
2. -mllvm is the parameter passing method of Clang, and --param is the parameter passing method of GCC
After the modification, KASan compilation and operation will be supported for Clang 18 and above
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
error: unpredictable STXR instruction, status is also a source
99 | "stxr %w0, %1, [%2] \n"
| ^
<inline asm>:5:10: note: instantiated into assembly here
5 | stxr w10, x10, [x9]
Using w0 to pass the result can cause the "status register is also a source" problem, resulting in unpredictable behavior.
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
The ARM64 instruction ADD has a 12-bit limit (0 - 4095) for immediate values, but here we try to use a symbolic address (.Linitparms) as an immediate value, which does not comply with the ARM64 instruction set rules.
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
common/arm64_cache.c:305:38: error: value size does not match register size specified by the constraint and modifier [-Werror,-Wasm-operand-widths]
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
A deadlock occurs for priv->lock when uart_xmitchars is called from
within imx9_txint. This is because uart_xmitchars does a callback to
imx9_txint and tries to acquire the lock again.
However, there is no reason to hold the lock over uart_xmitchars, as it
has its own lock for mutual exclusion. Only the UART device needs to
be protected, and priv->lock does that.
Signed-off-by: Ville Juven <ville.juven@unikie.com>
Use the flag CONFIG_ARCH_HAVE_PERF_EVENTS to detect whether the architecture specific code
provides the up_perf_* functions. Now it is mixed with CONFIG_ARCH_PERF_EVENTS, which should
select just whether the perf events (perf_*) are enabled for the configuration.
- drivers/timers/arch_alarm.c: Don't compile the up_perf_* functions here if the
CONFIG_ARCH_HAVE_PERF_EVENTS is defined
- arch/*/*_perf.c: Change CONFIG_ARCH_PERF_EVENTS -> CONFIG_ARCH_HAVE_PERF_EVENTS to
select whether architecture specific up_perf_* functions are provided
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
For the RTL8211F PHY, configuration of RX/TXDLY was missing.
At least on my i.MX93 EVK, this is necessary for transmission
to work (RXDLY defaults to true on the PHY).
This commit brings support for RGMII internal delay configuration
(on or off for both directions) and enables it on the i.MX93 EVK
board. The introduced Kconfig is set to default to 'n', to avoid
breaking the functionality of other, out-of-tree boards based on
i.MX93, running the RTL8211F PHY, or to avoid introducing
unnecessary code on boards running other PHYs.
Configuration of internal delay on other PHYs is not
implemented, and results in a warning (but no error).
Signed-off-by: George Poulios <gpoulios@census-labs.com>
MUX_ENET1_TXC was missing from both the EVK board
definition and the IO muxing configuration function
of the ENET1 driver. As a result, transmission does
not work (unless the muxing is set by default in some
board? -not the case with EVK). This commit adds the
configuration and adds the definition to i.MX93 EVK.
WARN: other, out-of-tree i.MX93 boards need to define
MUX_ENET1_TXC accordingly, otherwise build will break.
Signed-off-by: George Poulios <gpoulios@census-labs.com>
Boards that run the i.MX9 bootloader at EL1 must not touch EL3-only
configuration. Add Kconfig guards so that:
* DDR training (IMX9_DDR_TRAINING)
* FIQ decode support (ARM64_DECODEFIQ)
are selected only when ARCH_ARM64_EXCEPTION_LEVEL == 3.
Code in arm64_chip_boot() is also guarded with ARCH_ARM64_EXCEPTION_LEVEL == 3
Signed-off-by: Theodore Karatapanis <tkaratapanis@census-labs.com>
After `CONFIG_STACK_USAGE` enabled, no "*.su" file was generated, tools/showstack.sh output nothing.
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
This implements an interrupt-based SPI driver for the BCM2711 SPI
interfaces (excluding auxiliary SPI interfaces). Only tested on SPI0
since proprietary firmware does not initialize any other SPI interfaces,
and doing so will require reverse engineering.
- Add ELE command to initialize the ELE RNG context.
- Add ELE command to poll the readiness of the RNG
- Add ELE command to obtain random numbers.
- Replace AHAB_ prefixes with ELE_
- Cleanup header includes
- Added some explanatory comments on .../hardware/imx9_ele.h
Signed-off-by: Theodore Karatapanis <tkaratapanis@census-labs.com>
Or will be catch by codespell, when do checkpatch.sh
Also fix the relative comment file changed.
include/nuttx/scsi.h
drivers/syslog/ramlog.c
excluded as we have to modify field name in struct
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
- Added "infor" to .codespellrc ignore-words-list.
This term is used by NXP's ROMAPI naming conventions and is not a typo
in this context.
- This prevents CI/CD codespell checks from failing due to false positives.
Signed-off-by: Theodore Karatapanis <tkaratapanis@census-labs.com>
MMU initialization is redundant for bootloaders(BL2) that load TF‑A(BL31).
TF-A will ignore and overwrite any MMU configuration performed by BL2.
Additionally the MMU comes with a large memory footprint (~50 KB)
which could be precious for such setups.
When the MMU is disabled all the memory is treated as device memory and
all alignment faults generate exceptions (as opposed to normal memory when
MMU is enabled). For that reason we need to add -fno-builtin when compiling
with CONFIG_ARCH_USE_MMU != y to prevent alignment faults.
- Guard MMU initialization with CONFIG_ARCH_USE_MMU
- If CONFIG_ARCH_USE_MMU is not set add -fno-builtin which prevents alignment errors.
- Deliberately didn't try to replace CONFIG_ARCH_HAVE_MMU with CONFIG_ARCH_USE_MMU
occurrences, because this will break a lot of build targets that assume MMU without
guarding the MMU initialization.
Signed-off-by: Theodore Karatapanis <tkaratapanis@census-labs.com>
This adds support for the i.MX9 ROMAPI, allowing boot in a more
device agnostic and portable manner. The ROMAPI "natively" allows to:
- Query the boot device for information.
- Copy data from the boot device to RAM.
An extra functionality was added to ROMAPI to calculate
offsets of sequential AHAB containers.
The AHAB functionality is built on top of raw ELE primitives and allows to:
- Authenticate a container image.
- Release the authenticated container.
Signed-off-by: Theodore Karatapanis <tkaratapanis@census-labs.com>
This extends ELE API to:
- Authenticate i.MX container header.
- Verify container images.
- Release resources of the authenticated containers.
Signed-off-by: Theodore Karatapanis <tkaratapanis@census-labs.com>
So far NuttX has supported OP-TEE interfacing over
local and RPMsg sockets. This commit introduces support
for direct invocation of OP-TEE through arm SMCs. The
SMC transport is enabled through CONFIG_DEV_OPTEE_SMC.
This SMC implementation has been tested only with arm64,
OP-TEE rev 4.4.
Note that it does not support reverse direction RPCs,
i.e. from the Secure World to the Normal World to
something like optee supplicant. A basic RPC handling
skeleton is provided with implementation for some
basic functions (alloc/free mem, and foreign interrupts)
but no supplicant command handling.
(+one minor change s/parm/param in arch/arm64/include/syscall
to satisfy the spellchecker during PR)
Signed-off-by: George Poulios <gpoulios@census-labs.com>
Add kernel build (target imx93-evk:knsh) to i.MX93 EVK.
This target is preconfigured for use with AHAB boot (see
https://spsdk.readthedocs.io/en/latest/examples/ahab/imx93/imx93_ahab_uboot.html)
as a replacement of U-Boot proper (BL33 at EL2), hence
the load address is set to 0x80200000.
Signed-off-by: George Poulios <gpoulios@census-labs.com>
This makes units compatible with what Linux uses for SocketCAN bitrate
and allows representing usual Single Wire Can (SAE J2411) usual bitrates
of 33333 and 83333 bps.
Signed-off-by: Carlos Sanchez <carlossanchez@geotab.com>
Previously, SIOCSCANBITRATE brought the iterface up to ensure changes
where immediately applied. This was confusing, see
https://lists.apache.org/thread/g8d0m6yp7noywhroby5br4hxt3r4og2c
Now SIOCSCANBITRATE fails is interface is up.
All existing SocketCAN drivers updated.
Signed-off-by: Carlos Sanchez <carlossanchez@geotab.com>
Renaming "modlib" to "libelf" is more in line with the implementation content,
which makes it easier for individual developers to understand the capabilities of this module.
CONFIG_LIBC_MODLIB -> CONFIG_LIBC_ELF
Signed-off-by: chao an <anchao.archer@bytedance.com>
test:
1.use mps3-an547 build helloxx as module and run it
2.use qemu-armv7a:knsh test kernel build helloxx and run it
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
