Commit graph

23610 commits

Author SHA1 Message Date
Kerogit
100bbe620e arch/avr: make the linker obey DEBUG_LINK_MAP
This patch adds -Map linker flag to Toolchain.defs for AVR.
2025-05-08 15:58:18 +08:00
Kerogit
290f09934d arch/avr: enable eliminating unused sections with GCC
This patch marks host GCC toolchain option with ARCH_TOOLCHAIN_GCC,
enabling various other settings depending on it. One of the enabled
settings is DEBUG_OPT_UNUSED_SECTIONS.

This patch also adjusts compiler and linker flags based on the value
of DEBUG_OPT_UNUSED_SECTIONS so unused sections are removed
2025-05-08 15:58:18 +08:00
Kerogit
3b39101c82 arch/avr: decouple enabling of IOBJ/IPTR qualifiers from debugging
These qualifiers are useful on their own, not only when debugging-related
strings are flagged with them
2025-05-08 15:58:18 +08:00
Serg Podtynnyi
e54d5fffd6 arch/arm/rp23xx: add missing fpu init for smp cores
On SMP systems we should enable FPU on each core

FPU extenstion support must be enabled on each core as stated on 4.6.5
arm m33 devices generic user guide

Signed-off-by: Serg Podtynnyi <serg@podtynnyi.com>
2025-05-07 22:03:15 -03:00
Serg Podtynnyi
7c203a96af arch/arm/rp23xx: update USB PLL/VCO/FBDIV and usb setup
RP2350 datasheet and upstream pico-sdk suggests higher VCO freq to
better output stability.
Increase the VCO and update PLL divs according to specs and calculation.
Higher VCO freq is more stable, lower VCO freq is more power friendly.
Also it's possible to use 120/6/5 with VCO 1440MHz for USB PLL to even
higher output stability.
USB setup changes from rp2040
Must clear the MAIN_CTRL.PHY_ISO bit at startup and after power down
events.

Signed-off-by: Serg Podtynnyi <serg@podtynnyi.com>
2025-05-08 03:02:06 +02:00
Tyler Bennett
9fca766bd4 arch/arm/stm32f0l0g0: Add STM32G0 Flash driver.
Add arch files and Kconfig options to interface with the progmem
driver on STM32G0 MCUs.

Signed-off-by: Tyler Bennett <tbennett@2g-eng.com>
2025-05-07 21:37:25 -03:00
Tim Hardisty
f967a69748 arch/arm/sama5: Add code to report the reset reason
This adds the necessary code and function to allow a board to determine the reason for a reset. This is useful in NXboot, for example.

Signed-off-by: Tim Hardisty <timh@jti.uk.com>
2025-05-07 02:03:00 +08:00
Tiago Medicci Serrano
c22df41ca6 espressif: Add variable to override MCUboot version and URL
The version and the git repository of Espressif's MCUboot port can
be changed by setting the `MCUBOOT_VERSION` and `MCUBOOT_URL`
environment variables before running the `make bootloader` command.

Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
2025-05-07 01:51:40 +08:00
Serg Podtynnyi
95cc862794 arch/arm/rp23xx: fix watchdog, enable TICK blocks
On the RP2350, the watchdog receives its tick input from the
system-level ticks block, unlike the RP2040, where the watchdog includes
its own tick generator. Enable the TICK blocks, update the watchdog
routines.

Signed-off-by: Serg Podtynnyi <serg@podtynnyi.com>
2025-05-05 23:58:10 +08:00
Matteo Golin
ac583fc585 arch/arm/rp2040/gpio: Allow simultaneous selection of multiple interrupt modes.
The RP2040 chip supports 4 different GPIO interrupt modes. They can be
configured to be used simultaneously, although previously the NuttX
support only allowed one type of interrupt to be enabled per GPIO pin.
This allows up to all four to be selected without changing previous
behaviour.

Signed-off-by: Matteo Golin <matteo.golin@gmail.com>
2025-05-05 23:48:21 +08:00
Eren Terzioglu
5cc7046a7f arch/risc-v/espressif: Fix Serial IFLOW build issue
Serial IFLOW build error fixed for risc-v based Espressif devices

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-05-05 23:47:05 +08:00
Eren Terzioglu
929c6313ff arch/risc-v/espressif: Add RS485 support for esp32[c3|c6|h2]
Add RS485 support for Risc-V based Espressif devices

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-05-05 23:47:05 +08:00
Serg Podtynnyi
bc8a7f713d arch/arm/rp23xx: add dsp/fpu extensions support
Each Arm Cortex-M33 processor in RP2350 is configured with Single
precision FPU and DSP extension
2025-05-05 09:35:39 +08:00
Lars Kruse
fa719f52f6 fix(stm32h7): malformed compiler error message
The malformed compiler error message was added in the initial commit of
the stm32_rptun module (2fffd7dad6).
2025-05-05 09:32:31 +08:00
Lars Kruse
9afc9868f6 fix(kinetis): malformed define KINETIS_NSPI
The malformed defines were introduced in commit 91dd3306c8.
They affect only the following chips:
* MK64FX512VMD12
* MK64FN1M0VMD12
2025-05-05 09:32:31 +08:00
raiden00pl
dbeba61c3c arch/nrf53/nrf53_sdc.c: fix broken RPMSG HCI server
BT device should not be registered when RPMGS HCI server is enabled.
Broken server since 31605b6335.

Signed-off-by: raiden00pl <raiden00@railab.me>
2025-05-05 09:28:35 +08:00
p-szafonimateusz
76e1b80076 arch/sim: add CAN support based on host SocketCAN
Add CAN support for sim target based on host SocketCAN interface.

Tested with virtual CAN on Linux but should work also with hardware CAN cards supported by host.

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2025-05-03 11:26:08 +08:00
George Poulios
7ea8b59a59 boards/imx93-evk: kernel build for AHAB boot
Add kernel build (target imx93-evk:knsh) to i.MX93 EVK.
This target is preconfigured for use with AHAB boot (see
https://spsdk.readthedocs.io/en/latest/examples/ahab/imx93/imx93_ahab_uboot.html)
as a replacement of U-Boot proper (BL33 at EL2), hence
the load address is set to 0x80200000.

Signed-off-by: George Poulios <gpoulios@census-labs.com>
2025-05-03 11:25:54 +08:00
Serg Podtynnyi
464c0831ce arch/arm/rp23xx: fix not restart after TX error
Fix a bug that I2C driver can not transfer after TX abort error.
It caused by remaining NO_STOP flag status.
same as done in commit 0df0a10 for cxd56xx

Signed-off-by: Serg Podtynnyi <serg@podtynnyi.com>
2025-05-03 11:17:37 +08:00
Tyler Bennett
c84f7c630f arch/stm32f0l0g0: Add support for STM32G0B1xx
Adds Kconfig and modifies chip.h for STM32G0B1xx options.

Signed-off-by: Tyler Bennett <tbennett@2g-eng.com>
2025-05-02 15:01:45 +02:00
p-szafonimateusz
09a5a0e72e x86_64: support for stack canaries
Add support for stack canaries for x86.

This includes mostly fixes for TLS support that are required for stack canaries
in x86. The FSBASE register must be unique per thread so we have to keep it in
thread registers area.

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2025-04-30 13:42:56 +08:00
p-szafonimateusz
ee5d5a8080 arch/x86_64: add debug interface
add hardware debug interface for x86_64 which can be used with gdbstub

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2025-04-30 13:40:10 +08:00
nuttxs
c4506929e9 arch/esp32_partition.c: fix the issue of switching from Factory to OTA_1
with a fixed seq of 1, which causes ota_get_bootseq() to return ota_0.

The current solution is to directly use the target partition's number (num)
as next_seq to ensure the correct increment logic of seq. Ensure the formula
(seq-1) % OTA_DATA_NUM + OTA_IMG_BOOT_OTA_0 correctly maps to ota_0 or ota_1

Signed-off-by: nuttxs <zhaoqing.zhang@sony.com>
2025-04-28 22:23:16 +08:00
buxiasen
726683485f arch/arm/heap: add mmu.h fix not defined error when BUILD_KERNEL
fix PGTABLE_SIZE not defined in sama5d4-ek/knsh
Error: common/arm_allocateheap.c:177:11: error: 'PGTABLE_SIZE' undeclared (first use in this function); did you mean 'PGTABLE_L2_SIZE'?
  177 |   size -= PGTABLE_SIZE * CONFIG_SMP_NCPUS;
      |           ^~~~~~~~~~~~

Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2025-04-28 22:17:43 +08:00
buxiasen
05beacc799 arch/arm/heap: reserved memory for mmu table
When using ARCH_PGPOOL_PBASE, always have to reserver mmu table,
not be used for kernel heap

Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2025-04-28 22:17:43 +08:00
buxiasen
1f8eb18e1d arch/arm/goldfish: fix mmu not enabled when smp
If smp enabled, mmu default disabled in arm_head.S,
We have to re-enable it in arm_boot per-chip.
Causing knsh-smp failed with user-space memory access

Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2025-04-28 22:17:43 +08:00
buxiasen
9e313bddbf arch/arm/goldfish: copy mmu table when SMP
As out current design, each cpu manage task mmu table by insert
and erase like-behavior for arm32, have to per-cpu mmu-table when kernel
build.

Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2025-04-28 22:17:43 +08:00
buxiasen
37e853f102 arch/arm/qemu: copy mmu table from cpu0 when SMP
As out current design, each cpu manage task mmu table by insert
and erase like-behavior for arm32, have to per-cpu mmu-table when kernel
build.

Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2025-04-28 22:17:43 +08:00
buxiasen
d28c15bd06 arch/arm/qemu: fix mmu not enabled when smp
If smp enabled, mmu default disabled in arm_head.S,
We have to re-enable it in arm_boot per-chip.
Causing knsh-smp failed with user-space memory access

Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2025-04-28 22:17:43 +08:00
Kevin Zhou
fb5f27e984 xtensa/esp32s3: fix tickless mode timer unexpect interrupt handle
Signed-off-by: Kevin Zhou <kevin.zhou@sony.com>
2025-04-28 22:13:52 +08:00
Jinliang Li
5ce0e93637 arch/risc-v: save/restore fpu registers always when CONFIG_ARCH_LAZYFPU is off
To fix a fpu illegal instruction exception due to fcsr have invalid
rounding-mode,  restore fcsr/f0~f31 with a random value from stack because fpu
context is not save into stack when mstatus.fs is clean(not dirty).

The number of save/restore fpu context operations is not equal.
In fact, CONFIG_ARCH_LAZYFPU is a performance optimization mechanism aimed at
minimizing the saving and restoring of FPU registers. In some cases, it
may only need to be saved once but must be restored multiple times.
Therefore, this optimization mechanism dictates that saving cannot be
done on the stack; it must be stored at a fixed location(e.g. task
control block buffer), as the stack requires push/pop operations to be
matched.

In case of that CONFIG_ARCH_LAZYFPU is off, save/restore FPU registers
always into stack to avoid the above issues.

Signed-off-by: Jinliang Li <lijinliang1@lixiang.com>
2025-04-27 13:08:29 +08:00
Kerogit
dd828c8920 arch/avr: fixed PC load on chips with more than 128kB program memory
The code used subi instruction to decrement the Y pointer but this
instruction only affects a byte, not a word. Fixed it by using
pre-decrement in the LD instruction instead.
2025-04-27 13:07:45 +08:00
Kerogit
88a66f18e6 arch/avr: save RAMPZ register into thread context
On chips that have it, RAMPZ is part of the thread context
and needs to be saved as well.
2025-04-27 13:07:45 +08:00
Kerogit
958b18f25e arch/avr: fixed typo in Kconfig 2025-04-27 13:07:45 +08:00
Leo Chung
5a1426d632 risc-v/esp32h2:Fix bootloader flash compiler error.
Add missing bootloader_enable_qio_mode() function in flash_qio_mode.c when
CONFIG_ESPRESSIF_FLASH_MODE_QIO option is enabled.

Signed-off-by: Leo Chung <gewalalb@gmail.com>
2025-04-23 16:16:47 +08:00
Leo Chung
931d80683d risc-v/esp32c3:Fix bootloader flash compiler error.
Add missing bootloader_enable_qio_mode() function in flash_qio_mode.c when
CONFIG_ESPRESSIF_FLASH_MODE_QIO option is enabled.

Signed-off-by: Leo Chung <gewalalb@gmail.com>
2025-04-23 16:16:47 +08:00
Leo Chung
d314329792 risc-v/esp32c6:Fix bootloader flash compiler error.
Add missing bootloader_enable_qio_mode() function in flash_qio_mode.c when
CONFIG_ESPRESSIF_FLASH_MODE_QIO option is enabled.

Signed-off-by: Leo Chung <gewalalb@gmail.com>
2025-04-23 16:16:47 +08:00
Serg Podtynnyi
37a1748dd3 arch/arm/rp23xx: fix irq priority levels
The RP2350 datasheet (Table 198) states that IRQ priority levels are
represented using 4 bits

Signed-off-by: Serg Podtynnyi <serg@podtynnyi.com>
2025-04-22 20:59:42 -03:00
Serg Podtynnyi
c531de3329 arch/arm/rp23xx: Address the spinlock errata RP2350-E2
Due to Errata RP2350-E2 use only safe spinlocks during start and testset

Signed-off-by: Serg Podtynnyi <serg@podtynnyi.com>
2025-04-22 20:59:23 -03:00
simbit18
047a40917c Cmake: Implement CMake build of Tiva arch
added TI/Stellaris Tiva

CMake added tm4c1294-launchpad and tm4c123g-launchpad board

Signed-off-by: simbit18 <simbit18@gmail.com>
2025-04-19 08:53:18 -03:00
Filipe Cavalcanti
b8e9bc3313 arch/xtensa: fix build errors related to data types on ESP32|S2|S3
Fix format specifier macros after compiler type changes.

Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
2025-04-18 09:32:58 +08:00
Filipe Cavalcanti
0715c584b7 arch/xtensa: use compiler's definition of uint32 and int32
Modify types.h and inttypes.h to use the correct _int32_t and _uint32_t types.
Type is now defined according to recent compiler versions.

Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
2025-04-18 09:32:58 +08:00
Tiago Medicci Serrano
c566cf51a2 risc-v/esp32c3: Fix getting the flash mappings by openocd-esp32
This adds new fields to the metadata section used by MCUBoot.
The openocd-esp32 project requires these fields to properly map the
flash segments and enable using SW breakpoints and flash through
openocd-esp32.

Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
2025-04-18 02:25:14 +08:00
Tiago Medicci Serrano
2bbafcacc1 xtensa/esp32s3: Fix getting the flash mappings by openocd-esp32
This adds new fields to the metadata section used by MCUBoot.
The openocd-esp32 project requires these fields to properly map the
flash segments and enable using SW breakpoints and flash through
openocd-esp32.

Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
2025-04-18 02:25:14 +08:00
Tiago Medicci Serrano
31b6cdac6d xtensa/esp32s2: Fix getting the flash mappings by openocd-esp32
This adds new fields to the metadata section used by MCUBoot.
The openocd-esp32 project requires these fields to properly map the
flash segments and enable using SW breakpoints and flash through
openocd-esp32.

Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
2025-04-18 02:25:14 +08:00
Tiago Medicci Serrano
7a3e67d59a xtensa/esp32: Fix getting the flash mappings by openocd-esp32
This adds new fields to the metadata section used by MCUBoot.
The openocd-esp32 project requires these fields to properly map the
flash segments and enable using SW breakpoints and flash through
openocd-esp32.

Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
2025-04-18 02:25:14 +08:00
Filipe Cavalcanti
55fbf93c9c arch/risc-v: ADC support for ESP32-C3|C6|H2
Add common source for ADC that supports ESP32-C3|C6|H2.

Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
2025-04-17 13:56:40 +08:00
Filipe Cavalcanti
99099a1a9d arch/xtensa: ADC support on ESP32|S2|S3
Add common ADC source for ESP32|S2|S3.
Remove legacy ADC from ESP32S3.

Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
2025-04-17 13:56:40 +08:00
Carlos Sanchez
d976c66edf net: use bps units for bitrate in SocketCAN interfaces.
This makes units compatible with what Linux uses for SocketCAN bitrate
and allows representing usual Single Wire Can (SAE J2411) usual bitrates
of 33333 and 83333 bps.

Signed-off-by: Carlos Sanchez <carlossanchez@geotab.com>
2025-04-16 11:07:27 -03:00
simbit18
7af6b8c63d arch/arm/src/armv6-m/CMakeLists.txt: fix undefined reference to `up_show_cpuinfo'
Aligned Cmakefile with Make.defs PR #10132

fix

FAILED: nuttx
C:\WINDOWS\system32\cmd.exe /C "cd . && D:\nx20250410\tools\gcc-arm-none-eabi\bin\arm-none-eabi-gcc.exe  --specs=nosys.specs   -Wl,--print-memory-usage -Wl,--entry=__start -nostdlib -Wl,--gc-sections -Wl,--cref -Wl,-Map=nuttx.map @CMakeFiles\nuttx.rsp -o nuttx && cd ."
D:/nx20250410/tools/gcc-arm-none-eabi/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/bin/ld.exe: fs/libfs.a(fs_procfscpuinfo.c.obj): in function `cpuinfo_read':
D:/rp2040/nuttx/fs/procfs/fs_procfscpuinfo.c:160:(.text.cpuinfo_read+0xa): undefined reference to `up_show_cpuinfo'

Signed-off-by: simbit18 <simbit18@gmail.com>
2025-04-16 21:25:55 +08:00