- fix chip/imxrt_clockconfig_ver1.h:23: error: header guard '__ARCH_ARM_SRC_IMXRT_IMXRT_CLOCKCONFIG_VER1_H' followed by '#define' of a different macro [-Werror=header-guard]
Signed-off-by: simbit18 <simbit18@gmail.com>
the -ffunction-sections and -fdata-sections are also supported by
greenhills, and these two compile options can benefit with section
layout optimization, and thus reduce the final image size
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
According to the Greenhills documentation, the "-Wall" option is
deprecated for use. Instead, the "-ghstd=last" option is recommended.
Compared with "-Wall", the "-ghstd=last" option can capture more
warnings and has stricter rules.
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
In Green Hills, if the name of the file to be preprocessed ends with ".ld",
this file must be renamed to ".ld.i". Otherwise, the following error will be reported:
ccarm: Error: -o out/build/cmake_out/mann_dcu_evb_ghs_ap/gnu-elf.ld has wrong suffix for -P option (expect .i)
Currently, based on the documentation and actual operations, only files
ending with "*.ld" can trigger this preprocessing error. There are no such
issues in other cases.
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
Avoid the errno changed after interrupt in sim and make return value
mistake when according to errno.
Move host_errno_convert from macro to sim_errno.c.
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
We will remove the API in next commit, so remove the errno manual save
API and save errno more commonly.
After whole pull request, should no longer need to care about errno.
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
This reverts commit ac5b38c9e5.
Keep host_errno_convert as a common interface in sim_internal.h
Keep the up_irq_save & up_irq_restore as common interface
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
The TLS initialization logic needs to be updated to match the modified
linker script section definitions. The previous implementation assumed
that _END_TDATA and _START_TBSS were contiguous, but there may be
padding between these sections for alignment purposes.
This commit updates up_tls_initialize() to explicitly account for the
padding gap between _END_TDATA and _START_TBSS when zeroing the .tbss
section. The size calculation in up_tls_size() is also updated to use
_END_TBSS instead of the previous _END_TXXX definition to match the
current linker script layout.
Changes:
- Calculate padding gap: (_START_TBSS - _END_TDATA)
- Zero .tbss at correct offset accounting for padding
- Update size calculation to use proper section boundaries
Signed-off-by: guoshengyuan1 <guoshengyuan1@xiaomi.com>
Reimplement __aeabi_read_tp using naked function with inline assembly
to strictly follow ARM EABI TLS helper specification.
The ARM EABI specifies that __aeabi_read_tp may only modify r0, and
compilers rely on this guarantee by NOT saving r1-r3 registers when
calling this function. The previous simple C implementation could
potentially clobber these registers through compiler optimizations,
violating the ABI contract and causing subtle bugs.
Changes:
- Add __aeabi_read_tp_core() helper to allow tls_get_info() macro
expansion in C context
- Explicitly preserve r1-r3 registers per EABI requirement
This ensures proper register usage compliance for all calling contexts
while maintaining the ability to use tls_get_info() macro correctly.
Reference: ARM EABI TLS Helper Specification
https://github.com/ARM-software/abi-aa/blob/main/rtabi32/rtabi32.rst#thread-local-storage-new-in-v2-01
Signed-off-by: guoshengyuan1 <guoshengyuan1@xiaomi.com>
Ensure the CMake build explicitly locates and links libstdc++.a
when CONFIG_LIBCXXTOOLCHAIN is enabled. This aligns CMake behavior
with the Make build system and fixes STL/libc header conflicts
observed on xmc4800-relax:nsh.
Signed-off-by: trns1997 <trns1997@gmail.com>
Commit e5db83d7db introduced a change to the file updated by this patch
which caused a build-time warning about unused variable. This patch
removes declaration of the variable from the code.
This patch also updates comment that relates to what was changed
in the commit.
Patch was tested by building breadxavr:nsh - resulting binary is identical
(by SHA256 checksum) and the warning is no longer present.
Signed-off-by: Kerogit <kr.git@kerogit.eu>
Per further feedback from Litex community, the vexriscv cache is
write-through so no flush is required - therefore, make it a nop.
And add a pointer to vexriscv invalidation magic instr docs.
Signed-off-by: Justin Erenkrantz <justin@erenkrantz.com>
modify the code of the adapted protocol stack to avoid deadlocks and the
logic that cannot be protected by locks after modification.
Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
The riscv_vpuconfig() was defined but never called in qemu_rv_start. This caused mstatus.VS to remain disabled, leading to Illegal Instruction exceptions when the OS attempted to use vector registers. This patch adds the missing initialization call.
Signed-off-by: ENJOU1224 <enjou1224@outlook.com>
The riscv_savevpu/restorevpu functions were using 'uintptr_t *' for vector registers, but 'tcb->xcp.vregs' is defined as 'uintreg_t *'. This mismatch caused compilation errors on GCC 13+ due to incompatible pointer types. This patch aligns the parameter types to 'uintreg_t *'.
Signed-off-by: ENJOU1224 <enjou1224@outlook.com>
The USB driver framework only implements a single ISOC transfer.
If multiple transfers are needed, the class driver can initiate
multiple urbs to meet the real-time requirements of the ISOC
endpoint. The class driver's urb record the buf address, length,
and number of packets sent. The callback function calculates the
data location in the buf based on the callback number and length
returned.
Signed-off-by: yangsong8 <yangsong8@xiaomi.com>
On success, zero (OK) is returned. On a failure, a negated errno value
is returned indicating the nature of the failure.
Signed-off-by: yangsong8 <yangsong8@xiaomi.com>
The items is not used in up_flush_dcache, and we should use it in
function cache_invalidate_dcache_items.
Signed-off-by: rongyichang <rongyichang@xiaommi.com>
Most of the peripheral support matches litex vexriscv-smp.
* arch/risc-v/Kconfig: Defer RV32 selection to core as litex board can do RV64.
* arch/risc-v/src/litex/Make.defs
arch/risc-v/src/litex/hardware/litex_clint.h
arch/risc-v/src/litex/hardware/litex_memorymap.h
arch/risc-v/src/litex/hardware/litex_plic.h
arch/risc-v/src/litex/litex_irq.c
arch/risc-v/src/litex/litex_irq_dispatch.c: Add CONFIG_LITEX_CORE_VEXIIRISCV
conditional where vexriscv_smp conditionals are.
* boards/risc-v/litex/arty_a7/configs/nsh-vexii/defconfig: New config.
* boards/risc-v/litex/arty_a7/include/vexii_irq.h: vexiiriscv irq defintion.
* boards/risc-v/litex/arty_a7/include/vexii_memorymap.h: vexiiriscv memory map.
* boards/risc-v/litex/arty_a7/scripts/ld.script: Define __global_pointer for
toolchain happiness matching other RISC-V linker scripts.
(This commit was written with assistance from Claude Code.)
Signed-off-by: Justin Erenkrantz <justin@erenkrantz.com>
When compiling with O2 optimization, the compiler optimizes the code
in a way that causes irq variable to be corrupted. The getipsr()
function reads IPSR into r0, but the subsequent inline assembly that
sets FPSCR also uses r0 without declaring it as clobbered. This causes
the compiler to reuse r0 for the immediate value (0x40000), overwriting
the IRQ number read from IPSR.
The issue manifests as:
- getipsr() correctly reads IPSR (e.g., 0xf for IRQ 15)
- Compiler optimizes and reuses r0 for ARM_FPSCR_LTPSIZE_NONE (0x40000)
- irq variable gets the wrong value 0x40000 instead of actual IRQ number
- This leads to assertion failures in irq_dispatch due to invalid IRQ
Root cause analysis from disassembly:
mrs r0, IPSR ; Read IPSR to r0
mov.w r0, #262144 ; Compiler overwrites r0 with 0x40000!
vmsr fpscr, r0 ; Set FPSCR
str r0, [sp, #4] ; Store corrupted 0x40000 as irq
...
ldr r0, [sp, #4] ; Load corrupted value
bl irq_dispatch ; Call with wrong IRQ number 0x40000
Fix by adding r0 to the clobber list in the inline assembly, which
forces the compiler to save irq value before using r0 for FPSCR setup.
This issue only occurs at O2 optimization level and affects ARMv8-M
architecture with FPU enabled.
Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
This duplicates the up_invalidate_dcache_all as vexriscv's DBUS cache
does not distinguish between flushing and invalidation.
Signed-off-by: Justin Erenkrantz <justin@erenkrantz.com>
