Commit graph

13 commits

Author SHA1 Message Date
Marco Casaroli
52e84e0c0a arch/arm/rp23xx: Add hardware TRNG driver for /dev/random.
Add a driver for the rp2350 hardware true random number generator.

Enabling CONFIG_RP23XX_RNG selects ARCH_HAVE_RNG and builds the driver,
which registers /dev/random (and /dev/urandom when CONFIG_DEV_URANDOM
selects the architecture source, DEV_URANDOM_ARCH).  Each read enables
the entropy source, waits for a valid 192-bit entropy holding register
(EHR) sample, reads the six 32-bit EHR words, and repeats until the
request is satisfied.

Document the TRNG on the rp23xx platform page.

Assisted-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Signed-off-by: Marco Casaroli <marco.casaroli@gmail.com>
2026-07-25 15:06:56 +08:00
Jorge Guzman
26ec938064 risc-v/gd32vw55x: add GigaDevice GD32VW553 port (Wi-Fi 6)
New RISC-V chip port for the GigaDevice GD32VW55x (Nuclei N307, Wi-Fi 6
and BLE 5.3 combo), with the GD32VW553K-START board.

Core:
- ECLIC interrupt controller, clock tree (160 MHz / 40 MHz HXTAL),
  64-bit machine timer, serial (USART0/UART1/UART2) and RTC.
- The instruction cache must be enabled in head.S or the UART drops
  characters under load; the mask ROM uses the first 0x200 bytes of SRAM
  so the image is linked at 0x20000200; the RTC needs PMU_CTL0.BKPWEN or
  the register writes are silently discarded.
- The ECLIC only auto-clears the interrupt pending bit in hardware-vectored
  mode, so the trap dispatch clears it for edge-triggered sources or they
  re-fire forever (level-triggered peripherals clear their own).

Peripherals: DMA (8 channels), GPIO + EXTI, SPI (optional DMA), I2C0/I2C1
(the new STM32-v2-style IP, not the GD32F4 one), ADC, PWM and input
capture on the timers, both watchdogs, PROGMEM, TRNG and CRC.  All use
the standard NuttX lower-half interfaces and direct register access, not
the vendor SPL.  Three user LEDs (GPIOC), and a software reset through the
Nuclei SysTimer.

Internal flash: it is a system-in-package NOR die behind the real-time
decryption block, so it is not programmed through the FMC registers -- the
driver goes through the mask ROM API (rom_flash_*), the same way the
vendor code does.  PROGMEM can be mounted as LittleFS; the region sits
below the Wi-Fi NVDS and must not overlap it.

Wi-Fi (wlan0), station and softAP:
- The MAC/PHY, RF and WPA supplicant are linked as prebuilt BSD-3
  libraries.  They are RTOS-agnostic, so the OS binding is a sys_* facade
  on NuttX primitives (gdwifi/wrapper_nuttx.c).  Critical sections mask by
  ECLIC priority threshold, not by disabling every interrupt, or the MAC
  misses its microsecond deadlines.
- The lwIP stack of the SDK is not used: the interface is a
  netdev_lowerhalf driver driven by the standard tools (wapi, ifup, renew,
  ping, dhcpd).  EAPOL is handed to the supplicant instead of the IP
  stack.  The lowerhalf "priority" field is the work-queue id (HPWORK/
  LPWORK), not a task priority -- a wrong value makes receive() never run
  and every packet is dropped.
- The vendor gives the radio 32 KB of shared SRAM as an extra heap; this
  needs CONFIG_MM_REGIONS >= 2 or the kernel silently drops the region.
- The DHCP client needs CONFIG_NETUTILS_DHCPC_BOOTP_FLAGS=0x8000 so the
  server answers the OFFER by broadcast.
- softAP (wapi master mode -> wifi_management_ap_start): the single-VIF
  firmware does station or AP at a time.  Use WPA2, not WPA3: the SAE
  handshake is deep on the stack and overflows the elliptic-curve crypto
  with the default task stacks, so the Wi-Fi configs raise
  CONFIG_INIT_STACKSIZE/DEFAULT_TASK_STACKSIZE.

Vendor SDK: cloned by the build at "context" time, pinned to a validated
commit and patched in place -- so CI can build with nothing preinstalled,
the same pattern as esp-hal-3rdparty.  The prebuilt libraries are built
for the hard-float ilp32f ABI.

BLE 5.3, marked EXPERIMENTAL and off by default: the prebuilt libble is an
all-in-one controller plus RivieraWaves host (GAP/GATT/SMP inside the blob)
with no HCI transport, so the port drives the vendor host directly
(ble_adp_*, ble_adv_*, ble_gap_*) instead of registering a bt_driver_s.
The SDK's radio interrupt handlers must be attached to the NuttX IRQ table
(they are reached through the ECLIC hardware vector table in the vendor
build); attaching also keeps --gc-sections from dropping them.  It ships
with no configuration; enabling it advertises as "NuttX", connectable.

Boards: gd32vw553k-start with nsh, wapi, sta_softap, periph and littlefs
configurations, and the board added to the CI build list.

Tested on hardware (GD32VW553K-START): NSH, the peripheral drivers
(TRNG entropy and the LEDs exercised), LittleFS (write, read, survives a
reboot), the full Wi-Fi station path (scan, WPA2, DHCP, ping to the
internet), the softAP (a client associates with WPA2, gets an address
from the board's DHCP server, and pings the board), and BLE (advertises as
"NuttX"; a central connects and enumerates the GATT database).

Assisted-by: Claude Opus 4.8
Signed-off-by: Jorge Guzman <jorge.gzm@gmail.com>
2026-07-16 10:03:16 -03:00
Xiang Xiao
754dfd980b arch/sim: replace macOS C++ constructor runtime hack with post-link patch
The sim architecture needs to defer C++ global constructors until after
NuttX kernel initialization completes. On macOS this was previously done
via a runtime hack (sim_macho_init.c): a __attribute__((constructor))
function intercepted constructors, saved them, and replayed them later.
That approach was fragile because it depended on constructor ordering
and required mprotect() to patch the read-only __mod_init_func section
at runtime.

This commit replaces the runtime hack with a post-link patching scheme:

  1. Link with -Wl,-ld_classic,-no_fixup_chains to keep the classic
     __mod_init_func pointer format (prevents ld64 from converting it
     to __init_offsets).
  2. Post-link, run patch_macho_initsection.py (python3 + lief) to
     patch Mach-O section type flags from
     MOD_INIT_FUNC_POINTERS/INIT_FUNC_OFFSETS to REGULAR, so dyld
     skips them entirely.
  3. Use the Mach-O auto-generated boundary symbols
     section$start$__DATA_CONST$__mod_init_func /
     section$end$__DATA_CONST$__mod_init_func, mapped via __asm()
     labels in arch/sim/include/arch.h to the common _sinit[]/_einit[]
     names used by lib_cxx_initialize().

Linux behavior is unchanged.

Changes:
  - arch/sim/include/arch.h: add macOS __asm() declarations for
    _sinit/_einit
  - arch/sim/src/Makefile: drop sim_macho_init.c HEADSRC handling,
    always pass -ld_classic,-no_fixup_chains on macOS, run
    patch_macho_initsection.py after link when CONFIG_HAVE_CXXINITIALIZE
  - arch/sim/src/sim/CMakeLists.txt: same for the CMake build
  - arch/sim/src/patch_macho_initsection.py: new lief-based patcher
  - arch/sim/src/sim/posix/sim_macho_init.c: deleted (135-line hack)
  - libs/libc/misc/lib_cxx_initialize.c: remove
    macho_call_saved_init_funcs special case; single unified loop

Testing:
  - macOS (Ventura VM): verified lief patching with standalone test
    (test_sinit7) confirming the constructor is deferred past main()
    and only invoked when explicitly called via the _sinit/_einit loop.

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2026-05-19 07:08:55 -03:00
guoshengyuan1
f9111e8946 codespellrc: add ist to ignorelist
In Intel 64 architecture code, ist
fails the spell check of checkpatch.

Signed-off-by: guoshengyuan1 <guoshengyuan1@xiaomi.com>
2025-10-14 17:42:01 +08:00
Matteo Golin
f8e5d07477 docs/codeowners: Add preliminary code owner file
This code owner file is auto-generated by the Python script in tools/
based off the git logs. It will allow new contributors to get better
auto-suggestions for which reviewers to request on their PRs. It also
creates an easy way to track down authors of certain NuttX subsystems
when refactors/changes are to be made.

Signed-off-by: Matteo Golin <matteo.golin@gmail.com>
2025-09-05 19:53:06 -04:00
Mateusz Szafoni
ba3a79505e Revert "codespellrc: add ans to ignore words"
This reverts commit 5592dc75dc.

Signed-off-by: raiden00pl <raiden00@railab.me>
2025-09-03 09:56:01 +02:00
raiden00pl
5592dc75dc codespellrc: add ans to ignore words
ans is short for "Alert Notification Service" used in NimBLE.

Signed-off-by: raiden00pl <raiden00@railab.me>
2025-09-02 19:57:32 +02:00
Serg Podtynnyi
2e7f75f6e0 arch/risc-v/rp23xx-riscv: Add rp23xx RISC-V cores support (Hazard3)
Chip name   : rp23xx-rv
Board name  : raspberrypi-pico-2-rv
Arch        : risc-v

Changes from ARM rp23xx impl

- Linker script update
- ASM head start
- Update chip start
- New Hazard3 registers
- Remove rp23xx chip hw spinlocks/testset
- New irq handling (external IRQ interrupt Hazard3)
- New timerisr based on RISC-V std MTIME and alarm arch
- No SMP yet
- Tickless option
- Double size for idle, irq and main stacks
- Board reset via watchdog trigger

Signed-off-by: Serg Podtynnyi <serg@podtynnyi.com>
2025-08-11 08:56:27 +08:00
Lars Kruse
3ce85ca54e style: fix spelling in code comments and strings 2025-05-23 10:48:41 +08:00
raiden00pl
0ecaeb7efe .codespellrc: ignore IST
Ignore IST for codespell.
IST is the name of company but also register name used in x86

Signed-off-by: raiden00pl <raiden00@railab.me>
2025-05-17 12:16:54 +08:00
Theodore Karatapanis
0011f165ff style: fix typos required by ci-cd
- Added "infor" to .codespellrc ignore-words-list.
  This term is used by NXP's ROMAPI naming conventions and is not a typo
  in this context.
- This prevents CI/CD codespell checks from failing due to false positives.

Signed-off-by: Theodore Karatapanis <tkaratapanis@census-labs.com>
2025-05-09 19:21:17 +08:00
Alan Carvalho de Assis
5acfb995e0 codespell: Add RCALL 2025-05-08 15:58:18 +08:00
Lars Kruse
1efeb39da0 style: add codespell configuration for common spelling exceptions
This file can be extended in order to cover all spelling check
exceptions (perceived as misspellings).
2025-05-05 12:34:39 +08:00