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Correct conditional compilation

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2756 42af7a65-404d-4744-a932-0658087f49c3
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patacongo 2010-06-20 17:07:13 +00:00
parent 271b94a9e8
commit ff7790385b
1 changed files with 1 additions and 1 deletions
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arch/arm/src/lpc17xx/lpc17_clockconfig.c
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@ -104,7 +104,7 @@ void lpc17_clockconfig(void)
/* PLL0 is used to generate the CPU clock divider input (PLLCLK). */
#if CONFIG_LPC17_PLL0
#ifdef CONFIG_LPC17_PLL0
/* Select the PLL0 source clock, multiplier, and pre-divider values. NOTE that
* a special "feed" sequence must be written to the PLL0FEED register in order
* for changes to the PLL0CFG register to take effect.