mirror of
https://github.com/apache/nuttx.git
synced 2026-08-01 20:28:58 +00:00
!arm/stm32h7: standardize public API prefix to stm32_
BREAKING CHANGE: Public STM32H7 APIs were renamed from stm32h7_* forms to canonical stm32_* forms. Signed-off-by: raiden00pl <raiden00@railab.me>
This commit is contained in:
parent
8ece56ff11
commit
fe42e755a1
17 changed files with 86 additions and 88 deletions
|
|
@ -2277,7 +2277,7 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr,
|
|||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32h7_adc_initialize
|
||||
* Name: stm32_adc_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the ADC.
|
||||
|
|
@ -2302,9 +2302,8 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr,
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
struct adc_dev_s *stm32h7_adc_initialize(int intf,
|
||||
const uint8_t *chanlist,
|
||||
int cchannels)
|
||||
struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist,
|
||||
int cchannels)
|
||||
{
|
||||
struct adc_dev_s *dev;
|
||||
struct stm32_dev_s *priv;
|
||||
|
|
|
|||
|
|
@ -785,7 +785,7 @@ extern "C"
|
|||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32h7_adc_initialize
|
||||
* Name: stm32_adc_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the ADC.
|
||||
|
|
@ -801,9 +801,8 @@ extern "C"
|
|||
****************************************************************************/
|
||||
|
||||
struct adc_dev_s;
|
||||
struct adc_dev_s *stm32h7_adc_initialize(int intf,
|
||||
const uint8_t *chanlist,
|
||||
int nchannels);
|
||||
struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist,
|
||||
int nchannels);
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
|
|||
|
|
@ -137,14 +137,14 @@ static void stm32_cpu2sem_take(void)
|
|||
defined(CONFIG_STM32H7_CORTEXM4_ENABLED)
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32h7_start_cm4
|
||||
* Name: stm32_start_cm4
|
||||
*
|
||||
* Description:
|
||||
* Start CM4 core
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32h7_start_cm4(void)
|
||||
void stm32_start_cm4(void)
|
||||
{
|
||||
uint32_t regval = 0;
|
||||
|
||||
|
|
@ -177,14 +177,14 @@ void stm32h7_start_cm4(void)
|
|||
|
||||
#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM4
|
||||
/****************************************************************************
|
||||
* Name: stm32h7_waitfor_cm7
|
||||
* Name: stm32_waitfor_cm7
|
||||
*
|
||||
* Description:
|
||||
* Wait for CM7 core initialization
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32h7_waitfor_cm7(void)
|
||||
void stm32_waitfor_cm7(void)
|
||||
{
|
||||
if (stm32_cm4_boot() == true)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -54,26 +54,26 @@ extern "C"
|
|||
defined(CONFIG_STM32H7_CORTEXM4_ENABLED)
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32h7_start_cm4
|
||||
* Name: stm32_start_cm4
|
||||
*
|
||||
* Description:
|
||||
* Start CM4 core
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32h7_start_cm4(void);
|
||||
void stm32_start_cm4(void);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM4
|
||||
/****************************************************************************
|
||||
* Name: stm32h7_waitfor_cm7
|
||||
* Name: stm32_waitfor_cm7
|
||||
*
|
||||
* Description:
|
||||
* Wait for CM7 core initialization
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32h7_waitfor_cm7(void);
|
||||
void stm32_waitfor_cm7(void);
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
|
|
|
|||
|
|
@ -48,27 +48,27 @@ extern "C"
|
|||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32h7_flash_getopt
|
||||
* Name: stm32_flash_getopt
|
||||
*
|
||||
* Description:
|
||||
* Returns the current flash option bytes from the FLASH_OPTSR_CR register.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
uint32_t stm32h7_flash_getopt(void);
|
||||
uint32_t stm32_flash_getopt(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32h7_flash_optmodify
|
||||
* Name: stm32_flash_optmodify
|
||||
*
|
||||
* Description:
|
||||
* Modifies the current flash option bytes, given bits to set and clear.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32h7_flash_optmodify(uint32_t clear, uint32_t set);
|
||||
void stm32_flash_optmodify(uint32_t clear, uint32_t set);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32h7_flash_swapbanks
|
||||
* Name: stm32_flash_swapbanks
|
||||
*
|
||||
* Description:
|
||||
* Swaps banks 1 and 2 in the processor's memory map. Takes effect
|
||||
|
|
@ -76,37 +76,37 @@ void stm32h7_flash_optmodify(uint32_t clear, uint32_t set);
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32h7_flash_swapbanks(void);
|
||||
void stm32_flash_swapbanks(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32h7_flash_lock
|
||||
* Name: stm32_flash_lock
|
||||
*
|
||||
* Description:
|
||||
* Locks a bank
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int stm32h7_flash_lock(void);
|
||||
int stm32_flash_lock(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32h7_flash_unlock
|
||||
* Name: stm32_flash_unlock
|
||||
*
|
||||
* Description:
|
||||
* Unlocks a bank
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int stm32h7_flash_unlock(void);
|
||||
int stm32_flash_unlock(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32h7_flash_writeprotect
|
||||
* Name: stm32_flash_writeprotect
|
||||
*
|
||||
* Description:
|
||||
* Enable or disable the write protection of a flash sector.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int stm32h7_flash_writeprotect(size_t page, bool enabled);
|
||||
int stm32_flash_writeprotect(size_t page, bool enabled);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
|
|
|
|||
|
|
@ -2543,7 +2543,7 @@ static int qspi_hw_initialize(struct stm32h7_qspidev_s *priv)
|
|||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32h7_qspi_initialize
|
||||
* Name: stm32_qspi_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the selected QSPI port in master mode
|
||||
|
|
@ -2556,7 +2556,7 @@ static int qspi_hw_initialize(struct stm32h7_qspidev_s *priv)
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
struct qspi_dev_s *stm32h7_qspi_initialize(int intf)
|
||||
struct qspi_dev_s *stm32_qspi_initialize(int intf)
|
||||
{
|
||||
struct stm32h7_qspidev_s *priv;
|
||||
uint32_t regval;
|
||||
|
|
@ -2683,7 +2683,7 @@ errout_with_dmach:
|
|||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32h7_qspi_enter_memorymapped
|
||||
* Name: stm32_qspi_enter_memorymapped
|
||||
*
|
||||
* Description:
|
||||
* Put the QSPI device into memory mapped mode
|
||||
|
|
@ -2697,9 +2697,9 @@ errout_with_dmach:
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32h7_qspi_enter_memorymapped(struct qspi_dev_s *dev,
|
||||
const struct qspi_meminfo_s *meminfo,
|
||||
uint32_t lpto)
|
||||
void stm32_qspi_enter_memorymapped(struct qspi_dev_s *dev,
|
||||
const struct qspi_meminfo_s *meminfo,
|
||||
uint32_t lpto)
|
||||
{
|
||||
struct stm32h7_qspidev_s *priv = (struct stm32h7_qspidev_s *)dev;
|
||||
uint32_t regval;
|
||||
|
|
@ -2775,7 +2775,7 @@ void stm32h7_qspi_enter_memorymapped(struct qspi_dev_s *dev,
|
|||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32h7_qspi_exit_memorymapped
|
||||
* Name: stm32_qspi_exit_memorymapped
|
||||
*
|
||||
* Description:
|
||||
* Take the QSPI device out of memory mapped mode
|
||||
|
|
@ -2788,7 +2788,7 @@ void stm32h7_qspi_enter_memorymapped(struct qspi_dev_s *dev,
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32h7_qspi_exit_memorymapped(struct qspi_dev_s *dev)
|
||||
void stm32_qspi_exit_memorymapped(struct qspi_dev_s *dev)
|
||||
{
|
||||
struct stm32h7_qspidev_s *priv = (struct stm32h7_qspidev_s *)dev;
|
||||
|
||||
|
|
|
|||
|
|
@ -83,7 +83,7 @@ extern "C"
|
|||
****************************************************************************/
|
||||
|
||||
struct qspi_dev_s;
|
||||
struct qspi_dev_s *stm32h7_qspi_initialize(int intf);
|
||||
struct qspi_dev_s *stm32_qspi_initialize(int intf);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32l4_qspi_enter_memorymapped
|
||||
|
|
@ -101,9 +101,9 @@ struct qspi_dev_s *stm32h7_qspi_initialize(int intf);
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32h7_qspi_enter_memorymapped(struct qspi_dev_s *dev,
|
||||
const struct qspi_meminfo_s *meminfo,
|
||||
uint32_t lpto);
|
||||
void stm32_qspi_enter_memorymapped(struct qspi_dev_s *dev,
|
||||
const struct qspi_meminfo_s *meminfo,
|
||||
uint32_t lpto);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32l4_qspi_exit_memorymapped
|
||||
|
|
@ -119,7 +119,7 @@ void stm32h7_qspi_enter_memorymapped(struct qspi_dev_s *dev,
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32h7_qspi_exit_memorymapped(struct qspi_dev_s *dev);
|
||||
void stm32_qspi_exit_memorymapped(struct qspi_dev_s *dev);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
|
|
|
|||
|
|
@ -195,7 +195,7 @@ void __start(void)
|
|||
#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM4
|
||||
/* Wait for CM7 initialization done */
|
||||
|
||||
stm32h7_waitfor_cm7();
|
||||
stm32_waitfor_cm7();
|
||||
#endif
|
||||
|
||||
/* If enabled reset the MPU */
|
||||
|
|
@ -309,7 +309,7 @@ void __start(void)
|
|||
|
||||
/* Start CM4 core after clock configuration is done */
|
||||
|
||||
stm32h7_start_cm4();
|
||||
stm32_start_cm4();
|
||||
#endif
|
||||
|
||||
nx_start();
|
||||
|
|
|
|||
|
|
@ -508,14 +508,14 @@ static void stm32h7_save_flashopt(struct stm32h7_flash_priv_s *priv)
|
|||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32h7_flash_unlock
|
||||
* Name: stm32_flash_unlock
|
||||
*
|
||||
* Description:
|
||||
* Unlocks a bank
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int stm32h7_flash_unlock(size_t addr)
|
||||
int stm32_flash_unlock(size_t addr)
|
||||
{
|
||||
int ret = -ENODEV;
|
||||
struct stm32h7_flash_priv_s *priv = stm32h7_flash_bank(addr);
|
||||
|
|
@ -536,14 +536,14 @@ int stm32h7_flash_unlock(size_t addr)
|
|||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32h7_flash_lock
|
||||
* Name: stm32_flash_lock
|
||||
*
|
||||
* Description:
|
||||
* Locks a bank
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int stm32h7_flash_lock(size_t addr)
|
||||
int stm32_flash_lock(size_t addr)
|
||||
{
|
||||
int ret = -ENODEV;
|
||||
struct stm32h7_flash_priv_s *priv = stm32h7_flash_bank(addr);
|
||||
|
|
@ -564,14 +564,14 @@ int stm32h7_flash_lock(size_t addr)
|
|||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32h7_flash_writeprotect
|
||||
* Name: stm32_flash_writeprotect
|
||||
*
|
||||
* Description:
|
||||
* Enable or disable the write protection of a flash sector.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int stm32h7_flash_writeprotect(size_t block, bool enabled)
|
||||
int stm32_flash_writeprotect(size_t block, bool enabled)
|
||||
{
|
||||
struct stm32h7_flash_priv_s *priv;
|
||||
uint32_t setbits = 0;
|
||||
|
|
@ -605,14 +605,14 @@ int stm32h7_flash_writeprotect(size_t block, bool enabled)
|
|||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32h7_flash_getopt
|
||||
* Name: stm32_flash_getopt
|
||||
*
|
||||
* Description:
|
||||
* Returns the current flash option bytes from the FLASH_OPTSR_CR register.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
uint32_t stm32h7_flash_getopt(void)
|
||||
uint32_t stm32_flash_getopt(void)
|
||||
{
|
||||
struct stm32h7_flash_priv_s *priv;
|
||||
priv = stm32h7_flash_bank(STM32_FLASH_BANK1);
|
||||
|
|
@ -625,14 +625,14 @@ uint32_t stm32h7_flash_getopt(void)
|
|||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32h7_flash_optmodify
|
||||
* Name: stm32_flash_optmodify
|
||||
*
|
||||
* Description:
|
||||
* Modifies the current flash option bytes, given bits to set and clear.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32h7_flash_optmodify(uint32_t clear, uint32_t set)
|
||||
void stm32_flash_optmodify(uint32_t clear, uint32_t set)
|
||||
{
|
||||
struct stm32h7_flash_priv_s *priv;
|
||||
bool was_locked;
|
||||
|
|
@ -652,7 +652,7 @@ void stm32h7_flash_optmodify(uint32_t clear, uint32_t set)
|
|||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32h7_flash_swapbanks
|
||||
* Name: stm32_flash_swapbanks
|
||||
*
|
||||
* Description:
|
||||
* Swaps banks 1 and 2 in the processor's memory map. Takes effect
|
||||
|
|
@ -660,16 +660,16 @@ void stm32h7_flash_optmodify(uint32_t clear, uint32_t set)
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32h7_flash_swapbanks(void)
|
||||
void stm32_flash_swapbanks(void)
|
||||
{
|
||||
uint32_t opts = stm32h7_flash_getopt();
|
||||
uint32_t opts = stm32_flash_getopt();
|
||||
if (opts & FLASH_OPTCR_SWAPBANK)
|
||||
{
|
||||
stm32h7_flash_optmodify(FLASH_OPTCR_SWAPBANK, 0);
|
||||
stm32_flash_optmodify(FLASH_OPTCR_SWAPBANK, 0);
|
||||
}
|
||||
else
|
||||
{
|
||||
stm32h7_flash_optmodify(0, FLASH_OPTCR_SWAPBANK);
|
||||
stm32_flash_optmodify(0, FLASH_OPTCR_SWAPBANK);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -478,14 +478,14 @@ static void stm32h7_save_flashopt(struct stm32h7_flash_priv_s *priv)
|
|||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32h7_flash_unlock
|
||||
* Name: stm32_flash_unlock
|
||||
*
|
||||
* Description:
|
||||
* Unlocks a bank
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int stm32h7_flash_unlock(size_t addr)
|
||||
int stm32_flash_unlock(size_t addr)
|
||||
{
|
||||
int ret = -ENODEV;
|
||||
struct stm32h7_flash_priv_s *priv = stm32h7_flash_bank(addr);
|
||||
|
|
@ -506,14 +506,14 @@ int stm32h7_flash_unlock(size_t addr)
|
|||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32h7_flash_lock
|
||||
* Name: stm32_flash_lock
|
||||
*
|
||||
* Description:
|
||||
* Locks a bank
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int stm32h7_flash_lock(size_t addr)
|
||||
int stm32_flash_lock(size_t addr)
|
||||
{
|
||||
int ret = -ENODEV;
|
||||
struct stm32h7_flash_priv_s *priv = stm32h7_flash_bank(addr);
|
||||
|
|
@ -534,14 +534,14 @@ int stm32h7_flash_lock(size_t addr)
|
|||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32h7_flash_writeprotect
|
||||
* Name: stm32_flash_writeprotect
|
||||
*
|
||||
* Description:
|
||||
* Enable or disable the write protection of a flash sector.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int stm32h7_flash_writeprotect(size_t block, bool enabled)
|
||||
int stm32_flash_writeprotect(size_t block, bool enabled)
|
||||
{
|
||||
struct stm32h7_flash_priv_s *priv;
|
||||
uint32_t setbits = 0;
|
||||
|
|
@ -575,14 +575,14 @@ int stm32h7_flash_writeprotect(size_t block, bool enabled)
|
|||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32h7_flash_getopt
|
||||
* Name: stm32_flash_getopt
|
||||
*
|
||||
* Description:
|
||||
* Returns the current flash option bytes from the FLASH_OPTSR_CR register.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
uint32_t stm32h7_flash_getopt(void)
|
||||
uint32_t stm32_flash_getopt(void)
|
||||
{
|
||||
struct stm32h7_flash_priv_s *priv;
|
||||
priv = stm32h7_flash_bank(STM32_FLASH_BANK1);
|
||||
|
|
@ -595,14 +595,14 @@ uint32_t stm32h7_flash_getopt(void)
|
|||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32h7_flash_optmodify
|
||||
* Name: stm32_flash_optmodify
|
||||
*
|
||||
* Description:
|
||||
* Modifies the current flash option bytes, given bits to set and clear.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32h7_flash_optmodify(uint32_t clear, uint32_t set)
|
||||
void stm32_flash_optmodify(uint32_t clear, uint32_t set)
|
||||
{
|
||||
struct stm32h7_flash_priv_s *priv;
|
||||
bool was_locked;
|
||||
|
|
@ -622,7 +622,7 @@ void stm32h7_flash_optmodify(uint32_t clear, uint32_t set)
|
|||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32h7_flash_swapbanks
|
||||
* Name: stm32_flash_swapbanks
|
||||
*
|
||||
* Description:
|
||||
* Swaps banks 1 and 2 in the processor's memory map. Takes effect
|
||||
|
|
@ -630,16 +630,16 @@ void stm32h7_flash_optmodify(uint32_t clear, uint32_t set)
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32h7_flash_swapbanks(void)
|
||||
void stm32_flash_swapbanks(void)
|
||||
{
|
||||
uint32_t opts = stm32h7_flash_getopt();
|
||||
uint32_t opts = stm32_flash_getopt();
|
||||
if (opts & FLASH_OPTCR_SWAPBANK)
|
||||
{
|
||||
stm32h7_flash_optmodify(FLASH_OPTCR_SWAPBANK, 0);
|
||||
stm32_flash_optmodify(FLASH_OPTCR_SWAPBANK, 0);
|
||||
}
|
||||
else
|
||||
{
|
||||
stm32h7_flash_optmodify(0, FLASH_OPTCR_SWAPBANK);
|
||||
stm32_flash_optmodify(0, FLASH_OPTCR_SWAPBANK);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -79,7 +79,7 @@ int stm32_w25qxxx_setup(void)
|
|||
struct mtd_dev_s *mtd_dev;
|
||||
int ret = -1;
|
||||
|
||||
qspi_dev = stm32h7_qspi_initialize(0);
|
||||
qspi_dev = stm32_qspi_initialize(0);
|
||||
if (!qspi_dev)
|
||||
{
|
||||
_err("ERROR: Failed to initialize W25 minor %d: %d\n",
|
||||
|
|
|
|||
|
|
@ -171,7 +171,7 @@ int stm32_adc_setup(void)
|
|||
|
||||
/* Call stm32_adcinitialize() to get an instance of the ADC interface */
|
||||
|
||||
adc = stm32h7_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS);
|
||||
adc = stm32_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS);
|
||||
if (adc == NULL)
|
||||
{
|
||||
aerr("ERROR: Failed to get ADC1 interface\n");
|
||||
|
|
@ -203,7 +203,7 @@ int stm32_adc_setup(void)
|
|||
|
||||
/* Call stm32_adcinitialize() to get an instance of the ADC interface */
|
||||
|
||||
adc = stm32h7_adc_initialize(2, g_adc2_chanlist, ADC2_NCHANNELS);
|
||||
adc = stm32_adc_initialize(2, g_adc2_chanlist, ADC2_NCHANNELS);
|
||||
if (adc == NULL)
|
||||
{
|
||||
aerr("ERROR: Failed to get ADC2 interface\n");
|
||||
|
|
@ -235,7 +235,7 @@ int stm32_adc_setup(void)
|
|||
|
||||
/* Call stm32_adcinitialize() to get an instance of the ADC interface */
|
||||
|
||||
adc = stm32h7_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS);
|
||||
adc = stm32_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS);
|
||||
if (adc == NULL)
|
||||
{
|
||||
aerr("ERROR: Failed to get ADC3 interface\n");
|
||||
|
|
|
|||
|
|
@ -171,7 +171,7 @@ int stm32_adc_setup(void)
|
|||
|
||||
/* Call stm32_adcinitialize() to get an instance of the ADC interface */
|
||||
|
||||
adc = stm32h7_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS);
|
||||
adc = stm32_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS);
|
||||
if (adc == NULL)
|
||||
{
|
||||
aerr("ERROR: Failed to get ADC1 interface\n");
|
||||
|
|
@ -203,7 +203,7 @@ int stm32_adc_setup(void)
|
|||
|
||||
/* Call stm32_adcinitialize() to get an instance of the ADC interface */
|
||||
|
||||
adc = stm32h7_adc_initialize(2, g_adc2_chanlist, ADC2_NCHANNELS);
|
||||
adc = stm32_adc_initialize(2, g_adc2_chanlist, ADC2_NCHANNELS);
|
||||
if (adc == NULL)
|
||||
{
|
||||
aerr("ERROR: Failed to get ADC2 interface\n");
|
||||
|
|
@ -235,7 +235,7 @@ int stm32_adc_setup(void)
|
|||
|
||||
/* Call stm32_adcinitialize() to get an instance of the ADC interface */
|
||||
|
||||
adc = stm32h7_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS);
|
||||
adc = stm32_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS);
|
||||
if (adc == NULL)
|
||||
{
|
||||
aerr("ERROR: Failed to get ADC3 interface\n");
|
||||
|
|
|
|||
|
|
@ -157,7 +157,7 @@ int stm32_adc_setup(void)
|
|||
|
||||
/* Call stm32_adcinitialize() to get an instance of the ADC interface */
|
||||
|
||||
adc = stm32h7_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS);
|
||||
adc = stm32_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS);
|
||||
if (adc == NULL)
|
||||
{
|
||||
aerr("ERROR: Failed to get ADC1 interface\n");
|
||||
|
|
@ -188,7 +188,7 @@ int stm32_adc_setup(void)
|
|||
|
||||
/* Call stm32_adcinitialize() to get an instance of the ADC interface */
|
||||
|
||||
adc = stm32h7_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS);
|
||||
adc = stm32_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS);
|
||||
if (adc == NULL)
|
||||
{
|
||||
aerr("ERROR: Failed to get ADC3 interface\n");
|
||||
|
|
|
|||
|
|
@ -160,7 +160,7 @@ int stm32_adc_setup(int adcno)
|
|||
|
||||
/* Call stm32_adcinitialize() to get an instance of the ADC interface */
|
||||
|
||||
adc = stm32h7_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS);
|
||||
adc = stm32_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS);
|
||||
if (adc == NULL)
|
||||
{
|
||||
aerr("ERROR: Failed to get ADC1 interface\n");
|
||||
|
|
@ -191,7 +191,7 @@ int stm32_adc_setup(int adcno)
|
|||
|
||||
/* Call stm32_adcinitialize() to get an instance of the ADC interface */
|
||||
|
||||
adc = stm32h7_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS);
|
||||
adc = stm32_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS);
|
||||
if (adc == NULL)
|
||||
{
|
||||
aerr("ERROR: Failed to get ADC3 interface\n");
|
||||
|
|
|
|||
|
|
@ -157,7 +157,7 @@ int stm32_adc_setup(void)
|
|||
|
||||
/* Call stm32_adcinitialize() to get an instance of the ADC interface */
|
||||
|
||||
adc = stm32h7_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS);
|
||||
adc = stm32_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS);
|
||||
if (adc == NULL)
|
||||
{
|
||||
aerr("ERROR: Failed to get ADC1 interface\n");
|
||||
|
|
@ -188,7 +188,7 @@ int stm32_adc_setup(void)
|
|||
|
||||
/* Call stm32_adcinitialize() to get an instance of the ADC interface */
|
||||
|
||||
adc = stm32h7_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS);
|
||||
adc = stm32_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS);
|
||||
if (adc == NULL)
|
||||
{
|
||||
aerr("ERROR: Failed to get ADC3 interface\n");
|
||||
|
|
|
|||
|
|
@ -149,7 +149,7 @@ int stm32_adc_setup(void)
|
|||
|
||||
/* Call stm32_adcinitialize() to get an instance of the ADC interface */
|
||||
|
||||
adc = stm32h7_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS);
|
||||
adc = stm32_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS);
|
||||
if (adc == NULL)
|
||||
{
|
||||
aerr("ERROR: Failed to get ADC1 interface\n");
|
||||
|
|
@ -180,7 +180,7 @@ int stm32_adc_setup(void)
|
|||
|
||||
/* Call stm32_adcinitialize() to get an instance of the ADC interface */
|
||||
|
||||
adc = stm32h7_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS);
|
||||
adc = stm32_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS);
|
||||
if (adc == NULL)
|
||||
{
|
||||
aerr("ERROR: Failed to get ADC3 interface\n");
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue