From fb6661aaa4bc90d0fa40132c6748789d0c4ff51b Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 12 Dec 2014 07:43:32 -0600 Subject: [PATCH] STM32 OTGHS Device: Fix for OTGHS core working in FS mode. From Ken Pettit --- arch/arm/src/stm32/stm32_otghsdev.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/src/stm32/stm32_otghsdev.c b/arch/arm/src/stm32/stm32_otghsdev.c index beb6431a487..c7e7fdadc43 100644 --- a/arch/arm/src/stm32/stm32_otghsdev.c +++ b/arch/arm/src/stm32/stm32_otghsdev.c @@ -5132,6 +5132,14 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv) stm32_putreg(OTGHS_GAHBCFG_TXFELVL, STM32_OTGHS_GAHBCFG); + /* Set the PHYSEL bit in the GUSBCFG register to select the OTG HS serial + * transceiver: "This bit is always 1 with write-only access" + */ + + regval = stm32_getreg(STM32_OTGHS_GUSBCFG); + regval |= OTGHS_GUSBCFG_PHYSEL; + stm32_putreg(regval, STM32_OTGHS_GUSBCFG); + /* Common USB OTG core initialization */ /* Reset after a PHY select and set Host mode. First, wait for AHB master * IDLE state.